Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-01-12
2010-06-15
Lin, Sun J (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07739640
ABSTRACT:
In one embodiment, the invention is a method and apparatus for static timing analysis in the presence of a coupling event and process variation. One embodiment of a method for computing a statistical change in delay and slew due to a coupling event between two adjacent nets in an integrated circuit design includes conducting a statistical timing analysis of the integrated circuit design, computing a statistical overlap window between the adjacent nets, where the statistical timing window represents a period of time during which signals on the adjacent nets can switch contemporaneously and computing the statistical change of delay due to the coupling event, in accordance with the statistical overlap window.
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Abbaspour Soroush
Schaeffer Gregory M.
Visweswariah Chandramouli
International Business Machines - Corporation
Lin Sun J
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