Electrical computers and digital processing systems: processing – Processing control
Reexamination Certificate
2008-04-29
2008-04-29
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Reexamination Certificate
active
07366881
ABSTRACT:
A method and apparatus are disclosed for staggering execution of an instruction. According to one embodiment of the invention, a single macro instruction is received wherein the single macro instruction specifies at least two logical registers and wherein the two logical registers respectively store a first and second packed data operands having corresponding data elements. An operation specified by the single macro instruction is then performed independently on a first and second plurality of the corresponding data elements from said first and second packed data operands at different times using the same circuit to independently generate a first and second plurality of resulting data elements. The first and second plurality of resulting data elements are stored in a single logical register as a third packed data operand.
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I
Boswell Brent R.
Hinton Glenn J.
Menezes Karol F.
Roussel Patrice
Thakkar Shreekant S.
Blakely , Sokoloff, Taylor & Zafman LLP
Coleman Eric
Intel Corporation
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