Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
2006-05-02
2006-05-02
Nguyen, T (Department: 2187)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
C711S204000, C711S205000, C711S154000, C711S155000
Reexamination Certificate
active
07039788
ABSTRACT:
Methods and apparatus for splitting a single logical block into two or more physical blocks are disclosed. According to one aspect of the present invention, a method for associating a plurality of physical blocks of a non-volatile memory with a logical block that includes of logical block elements involves grouping the logical block elements into at least a first logical set and a second logical set. Data associated with the first logical set is provided to a first physical block, and data associated with the second logical set is provided to a second physical block.
REFERENCES:
patent: 5222109 (1993-06-01), Pricer
patent: 5297148 (1994-03-01), Harari et al.
patent: 5388083 (1995-02-01), Assar et al.
patent: 5438573 (1995-08-01), Mangan et al.
patent: 5568439 (1996-10-01), Harari
patent: 5598370 (1997-01-01), Niijima et al.
patent: 5734816 (1998-03-01), Niijima et al.
patent: 5835935 (1998-11-01), Estakhri et al.
patent: 5845313 (1998-12-01), Estakhri et al.
patent: 5860082 (1999-01-01), Smith et al.
patent: 5907856 (1999-05-01), Estakhri et al.
patent: 5924113 (1999-07-01), Estakhri et al.
patent: 5987573 (1999-11-01), Hiraka
patent: 6016275 (2000-01-01), Han
patent: 6081447 (2000-06-01), Lofgren et al.
patent: 6115785 (2000-09-01), Estakhri et al.
patent: 6125435 (2000-09-01), Estakhri et al.
patent: 6139177 (2000-10-01), Venkatraman et al.
patent: 6230233 (2001-05-01), Lofgren et al.
patent: 6260156 (2001-07-01), Garvin et al.
patent: 6381176 (2002-04-01), Kim et al.
patent: 6405295 (2002-06-01), Bando
patent: 6426893 (2002-07-01), Conley et al.
patent: 6684289 (2004-01-01), Gonzalez et al.
patent: 6807095 (2004-10-01), Chen et al.
patent: 6823526 (2004-11-01), Howard et al.
patent: 6930193 (2005-08-01), Yaghi et al.
patent: 2001/0010065 (2001-07-01), Chiba
patent: 2002/0099904 (2002-07-01), Conley
patent: 62-283496 (1987-12-01), None
patent: 62-283497 (1987-12-01), None
patent: WO 02/058074 (2002-07-01), None
Kim, Jesung et al., “A Space-Efficient Flash Translation Layer for Compactflash Systems”, IEEE Transactions on Consumer Electronics, vol. 48, No. 2, May 2002.
Chang Robert C.
Qawami Bahman
Sabet-Sharghi Farshid
Anderson Levine & Lintel
Nguyen T
SanDisk Corporation
LandOfFree
Method and apparatus for splitting a logical block does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for splitting a logical block, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for splitting a logical block will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3554663