Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent
1997-08-19
2000-09-12
De Cady, Albert
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
714779, 341 94, H03M 1300
Patent
active
061192627
ABSTRACT:
In decoding an received codeword encoded for error correction purposes, a method for computing error locator polynomial and error evaluator polynomial in the key equation solving step is presented whereby the polynomials are generated through a number of intermediate steps that can be implemented with minimal amount of hardware circuitry. The number of intermediate steps requires a corresponding number of cycles to complete the calculation of the polynomials. Depending on the selected (N, K) code, the number of cycles required for the calculation of the polynomials would be within the time required for the calculation of up-stream data. More specifically, an efficient scheduling of a small number of finite-field multipliers (FFM's) without the need of finite-field inverters (FFI's) is disclosed. Using these new methods, an area-efficient architecture that uses only three FFM's and no FFI's is presented to implement a method derived from the inversionless Berlekamp-Massey algorithm. This method and architecture can be applied to a wide variety of RS and BCH codes with suitable code sizes.
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James L. Massey, "Shift-Register Synthesis and BCH Decoding", IEEE Transactions on Information Theory, vol. IT-15, No. 1, Jan. 1969, pp. 122-127.
Chang Hsie-Chia
Shung Chuen-Shen Bernard
Cady Albert De
Chang Emil
Greene Jason
Hamrick Claude A. S.
Shung Chuen-Shen Bernard
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