Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-08-14
2007-08-14
Dinh, Paul (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000, C703S002000
Reexamination Certificate
active
10643050
ABSTRACT:
An approach to solving combinational constraints, comprising compile and generate phases, is presented. The compile phase constructs successive sets of constraints, each with a solution generator, according to blocks of a partition of the constraints' random variables. Interleaving conjunction of the constraints, with existential quantification of the constraints, is attempted. The generate phase uses a reverse-order, block-by-block, process for solving constraints, where variables of each solution generator processed have been predetermined, by the processing of earlier blocks, except for the random variables of the current block. The present invention can be used in conjunction with image computation. Successive sets of reachable states of an FSM at successive time steps can be determined by successive applications of the compile phase, with each set of solution generators being saved. The sets of solution generators permit a backward sequence of states, from an error state back to a start state, to be determined.
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Dinh Paul
Park Vaughan & Fleming LLP
Rossoshek Helen
Synopsys Inc.
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