Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-09-12
2006-09-12
Thompson, A. M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
07107553
ABSTRACT:
A decomposition technique, for solving combinational constraint expressions, is presented. Decomposing a set of constraints can increase the opportunities for dividing them into independent sets that do not need to be conjoined in a constraint-solving process using a BDD representation. An AND decomposition, relying on a Theorem 1, is presented. An OR decomposition, relying on a corollary of Theorem 1, is presented. Theorem 1 provides an operation to test for, and create, a pair of sub-constraints G and H which are independent in any two variables x0and x1. A decomposition procedure is presented for separating as many variables as possible, of an input constraint, into disjoint sub-constraints. A merging procedure is presented, that can be used if a decomposition does not only contain constraints whose support sets are disjoint from each other. The decomposition procedure can also be used to identify hold constraints.
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Damiano Robert F.
Kukula James Herbert
Lockyear Brian Eugene
Pixley Carl Preston
Kaplan Jonathan T.
Rossoshek Helen
Synopsys Inc.
Thompson A. M.
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