Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-03-31
2002-09-03
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06446251
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of electronic design automation and, in particular, to a method and apparatus for socket-based design with reusable intellectual property.
2. Background Information
In the design of a common electronic system containing multiple interconnected components, a substantial amount of detailed connection information is required when using traditional design methodologies such as schematic capture, hardware description languages and netlist formats.
In an example where a single core is connected to a system bus, the designer typically is required to be aware of a wide range of design details such as knowledge of read lines, write lines, requests & acknowledges, the width of the address and data buses, where the core needs to map into the address space, what range of addresses it needs, and so on. Once the core is defined, the designer proceeds to connect nets and buses in a one-by-one fashion and manually assigns a net name to each connection. Multiply this connection information by the number of cores interacting in a typical system and the result is a system that is difficult to create and maintain.
Thus, a need exists for a convenient method of describing a high-level system through the assembly of lower-level components while isolating the system designer from much of the connection information required by conventional methods.
SUMMARY OF THE INVENTION
In accordance with the teachings of the present invention, a method and apparatus for socket-based design with reusable-IP is presented. In particular, in accordance with one embodiment of the present invention, a first set of one or more terminals of a first core are represented as a first socket having a first signature value. A second set of one or more terminals of a second core are represented as a second socket having a second signature value. The first socket is then automatically associated with the second socket based at least in part on a relationship between the first and second signature values.
REFERENCES:
patent: 6269467 (2001-07-01), Chang et al.
Gardner David Neal
Garner Robert E.
Blakely , Sokoloff, Taylor & Zafman LLP
Levin Naum B
Siek Vuthe
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