Electronic digital logic circuitry – Interface – Current driving
Patent
1997-03-24
1999-04-27
Santamauro, Jon
Electronic digital logic circuitry
Interface
Current driving
326 83, 326 30, 327170, H03K 190185
Patent
active
058983210
ABSTRACT:
A method and an apparatus for adjusting the slew rate and impedance of a buffer in an integrated circuitry. In one embodiment, an integrated circuit buffer includes a pre-driver circuit, which includes a slew rate compensation circuit, coupled to a driver circuit, which includes an impedance compensation circuit. The slew rate compensation circuit includes parallel connected p-channel transistors to power and parallel connected n-channel transistors to ground to provide a variable resistance to virtual rails for inverter circuits that are included in the pre-driver circuit. The slew rate compensation circuit is digitally controlled with slew rate control signals. The impedance compensation circuit includes parallel connected p-channel transistors to power and parallel connected n-channel transistors to ground from an output node of the buffer. The parallel connected transistors of the impedance compensation circuit are digitally controlled with impedance control signals. The resistance to power and ground from the respective rails of the pre-driver circuit are controlled with the slew rate control signals to adjust the slew rate of data signals being driven by the buffer. The rails are shared among the inverters of the driver circuit to reduce the number of devices used by the buffer, thereby reducing the amount of circuit area and power used by the buffer.
REFERENCES:
patent: 4719369 (1988-01-01), Asono et al.
patent: 4975598 (1990-12-01), Borkar
patent: 5013940 (1991-05-01), Ansel
patent: 5063308 (1991-11-01), Borkar
patent: 5216289 (1993-06-01), Hahn et al.
patent: 5231311 (1993-07-01), Ferry et al.
patent: 5528166 (1996-06-01), Ikbahar
patent: 5568081 (1996-10-01), Lui et al.
patent: 5594371 (1997-01-01), Douseki
patent: 5602494 (1997-02-01), Sundstrom
Donnelly KS et al.: A 660 MB/s Interface Megacell Portable Circuit in 0.3 .mu.m CMOS ASIC, IEEE J of Solid-State Circuits, vol. 31 (12): Dec. 1996.
Gabara TJ et al.: Forming Damped LRC Parasitic Circuits in Simultaneously Switched CMOS Output Buffers, IEEE J of Solid-State Circuits, vol. 32(3), Mar. 1997.
Ilkbahar Alper
Kleveland Bendik
Intel Corporation
Le Don Phu
Santamauro Jon
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