Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...
Reexamination Certificate
2007-02-20
2007-02-20
Perveen, Rehana (Department: 2116)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
C713S601000, C713S400000, C713S401000, C713S500000, C713S503000
Reexamination Certificate
active
10194765
ABSTRACT:
An adjustable logic circuit includes a pulse filter and delay circuit, a state machine and combinational logic circuit, and a data strobe generation circuit. The pulse filter and delay circuit is operative to read an adjustable configuration value and, based thereon, to implement a delay between an internal clock and both a data signal and a data strobe signal, the delay being a fraction of a clock period. The state machine and combinational logic circuit are operative to select a data value from a plurality of data values, and to provide a data signal based upon the data value. The data strobe generation circuit is operative to provide the data strobe signal at a time when both the data signal is valid and the delay is compatible with a predetermined external device.
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patent: 6453402 (2002-09-01), Jeddeloh
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Nunez Jose M.
Thomas, Jr. Thomas L.
Welker James A.
Brown Michael J.
Freescale Semiconductor Inc.
King Robert L.
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