Method and apparatus for simultaneous memory subarray testing

Details Method and apparatus for simultaneous memory subarray testing Method and apparatus for simultaneous memory subarray testing

1997-06-30

1999-03-16

Nelms, David

Static information storage and retrieval

Addressing

Multiplexing

36518902, 365201, 36523003, G11C 800

Patent

active

058838490

ABSTRACT:
One row of memory cells per sense amplifier bank on a multiple subarray dynamic random access memory (DRAM) are fired while in a test mode. Multiplexors are provided on local I/O lines to ensure that the local I/O lines are not connected to global I/O lines when multiple rows are fired. This provides protection for I/O circuitry not designed to handle the load of multiple local I/O lines coupled in parallel. The multiplexors are controlled by a multiplexor control signal which is separate from row and column decode signals. During a refresh/hammer test, such rows are fired as many times as possible during a refresh period. Then adjacent rows are tested to determine if they were affected by the firing. During the firing, the multiplexors effectively isolate global I/O lines from local I/O lines.

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