Method and apparatus for simultaneous, interleaved access of mul

Details Method and apparatus for simultaneous, interleaved access of mul Method and apparatus for simultaneous, interleaved access of mul

1992-10-22

1993-07-06

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

Simultaneous operations

36523001, G11C 1300

Patent

active

052260100

ABSTRACT:
A memory system having multiple memories and multiple ports. Multiplexing logic couples each of the ports to each of the memories. A sequencing circuit controls the multiplexers so that each port is sequentially coupled to each of the memories in sequence in a repeating cycle. When coupled to each memory, a block of data is transferred. A second port is coupled to a different memory at each point in time, with the two ports being switched simultaneously to avoid overlap. A port desiring access to the system must wait until it can fit into this switching queue so that it can transfer in lock-step with the other ports to a different memory. Each port has a data I/O bus, an address input bus, an address counter and R/W controls.

REFERENCES:
patent: 5097118 (1992-03-01), Iijima

Affiliated with

Also associated with

Rating

Method and apparatus for simultaneous, interleaved access of mul does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and apparatus for simultaneous, interleaved access of mul, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for simultaneous, interleaved access of mul will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1695105