Method and apparatus for simulation of a multi-processor circuit

Details Method and apparatus for simulation of a multi-processor circuit Method and apparatus for simulation of a multi-processor circuit

1996-10-18

2000-01-11

Teska, Kevin J.

39550047, G06F 1126, G06F 1516

Patent

active

060145129

ABSTRACT:
Multiple processor circuit simulator comprising a debugger interface, a synchronizer, a RISC processor simulator, a vector processor simulator, a shared memory, a co-processor interface module and an events module. The multiple processor simulator tightly couples the RISC processor simulator and vector processor simulator into a single executable process and a single address space. The synchronizer interleaves simulation of instruction execution between multiple processor simulators. The synchronizer determines which processor simulator to execute based on a furthest-behind clocking scheme. The clocking scheme is implemented by comparing the values held in clock simulators corresponding to the processor simulators.

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patent: 5758176 (1998-05-01), Agarwal et al.
Bagrodia et al., The Maisie Environment for Parallel Simulation, IEEE, pp. 4-12, 1994.
Apduhan et al., Experiments of a Reconfigurable Multiprocessor Simulation on a Distributed Environment, IEEE, pp. 539-546, 1992.
Braunl, Designing Massively Parallel Algorithms with Parallaxis, IEEE. pp. 612-617, 1991.
Eric Reither et al., (Article entitled "Simulating Networks of Superscalar Processors", 1994 IEEE, pp. 125-133), 1994.

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