Static information storage and retrieval – Systems using particular element – Ferroelectric
Reexamination Certificate
2003-01-30
2004-04-20
Le, Vu A. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Ferroelectric
C365S149000, C365S230050, C365S189040, C365S189011
Reexamination Certificate
active
06724645
ABSTRACT:
FIELD OF THE INVENTION
The invention is directed towards semiconductor memory circuits, and more specifically, towards a method and apparatus for shortening the read operations of destructive read memory circuits.
BACKGROUND OF THE INVENTION
FIG. 1A
shows a prior art “one transistor, one capacitor” (1T1C) memory cell
10
, the basic building block for ferroelectric random-access memories (FeRAMs). The 1T1C memory cell
10
has a single transistor M
1
connected in series to one terminal of a ferroelectric capacitor Cfe. The other terminal of the ferroelectric capacitor Cfe is connected to a plateline PL. The gate of the transistor M
1
is connected to a word line WL, while the source of the transistor M
1
is connected to a bitline BL.
Two basic operations are used to access the 1T1C memory cell
10
: a write and a read operation. During a write operation, the data value is placed on the bitline BL, and the word line WL is asserted. Then, the plateline PL is pulsed to store the data value on the ferroelectric capacitor C
fe
. For more detailed information about the operation of a FeRAM cell, please see “A Survey of Circuit Innovations in Ferroelectric Random-Access Memories” by A. Sheikholeslami and P. Glenn Gulak, Proceedings of the IEEE, Volume 88, No. 5, May 2000.
During a read operation, the bitline BL is first pre-charged to a predetermined known value. Then, the word line WL and then the plateline PL are asserted. The charge on the bitline BL is redistributed between the bitline BL and the capacitor C
fe
, resulting in a voltage swing on the bitline BL. The magnitude of this voltage swing indicates the value of the data previously stored on the capacitor C
fe
. The voltage swing is typically small and needs to be amplified to full rail, using a sense amplifier. The read operation is a destructive process, since the value stored must be overwritten in order to determine its value. The original stored value must be preserved elsewhere, and then written back to the memory cell after a read operation is performed. This write-back process is known as a “rewrite.” The read operation is typically much slower than the write operation, since it takes time for the charge redistribution to take place and settle to a final value.
To construct a memory, the 1T1C memory cells
10
are arranged into one or more large arrays, a design structure that is well known in the art. Each array consists of multiple rows of words, a “word” being the basic unit for reading from and writing to the memory. Only a single word can be selected for reading from or writing to an array at any given time. For detailed information on memory arrays, please see chapter 10 of “Digital Integrated Circuits: A Design Perspective” by Jan M. Rabaey, Upper Saddle River, N.J., Prentice-Hall, Inc., 1996.
FIG. 1B
shows a flowchart of two consecutive clock cycles, cycle N and cycle N+1, for a FeRAM made of an array of cells such as 1T1C memory cell
10
. Cycle N is a read operation. A memory address is selected in step
101
. In step
103
, the word is ready and available for reading. Finally, in step
105
, the word is restored to the memory during the rewrite. Step
107
begins cycle N+1 and the start of the next read or write operation.
As mentioned previously, the read operation takes much longer than the write operation. To accommodate the length of the read operation, a long clock cycle must be used. However, since the clock cycle is inversely proportional to the speed of the memory, a memory built using 1T1C memory cells is relatively slow.
SUMMARY OF THE INVENTION
In accordance with a preferred embodiment of the present invention, a method for shortening the read operation in a destructive read memory is disclosed. The read operation is shortened by omitting the rewrite step and delaying it to the subsequent clock cycle, when a new operation is initiated. Since the read operation is typically the longest operation for a memory cell, shortening the read operation also results in a shorter clock cycle and faster memory.
To simultaneously perform both the rewrite step as well as a subsequent operation, a FeRAM memory cell must have two ports. This FeRAM memory cell is also known as a “two transistor, one capacitor” (2T1C) memory cell. When the 2T1C memory cell is arrayed in a memory, the memory will have two sets of ports. The first set of ports accesses the same memory cells as the second set of ports. This allows two different words to be accessed in the memory at the same time.
A first set of ports is used to read a word during a read operation in a first clock cycle. In the subsequent clock cycle, a read or write operation begins simultaneously as the rewrite step begins. The rewrite step finishes rewriting the word through the first set of ports, where the read operation was initiated. Meanwhile, the subsequent clock cycle and operation use the second set of ports, without conflicting with the rewrite process that is finishing up through the first set of ports. By alternating the sets of ports used in each clock cycle, the rewrite step can always be delayed to the subsequent clock cycle. This method “hides” the rewrite step behind the next operation, thus shortening the time needed for a read operation. Hereinafter, this method will be known as the “alternating port method”.
Another method for shortening the clock cycle in a destructive read memory is disclosed. The read operation is shortened by omitting the rewrite step, delaying it to the subsequent clock cycle, and implementing the rewrite as a write operation. All read operations are initiated through one set of ports, while the second set of ports is reserved exclusively for write operations and rewrites. This method shall be referred to hereinafter as the “fixed port method”.
In an alternate embodiment, a DRAM memory cell can also be equipped with two transistors to implement the methods disclosed above. This concept of using two transistors can be applied to any destructive read charge-based memory scheme that currently uses a 1T1C structure.
REFERENCES:
patent: 5121353 (1992-06-01), Natori
patent: 5841695 (1998-11-01), Wik
patent: 5856940 (1999-01-01), Rao
patent: 5923593 (1999-07-01), Hsu et al.
patent: 6044034 (2000-03-01), Katakura
patent: 6510075 (2003-01-01), Jain
“Digital Integrated Circuits: A Design Perspective.” Jan M. Rabaey Prentice Hall, Inc. 1996 Upper Saddle River, NJ Ch. 10 pp. 551-621.
“A Survey of Circuit Innovations in Ferroelectric Random-Access Memories.” Ali Sheikholeslami & Glenn Gulak Proceedings of the IEEE, vol. 88, No. 5, May 2000.
Lanham Ralph H.
Pietromonaco David Victor
Agilent Technologie,s Inc.
Le Vu A.
Shie Judy Liao
LandOfFree
Method and apparatus for shortening read operations in... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for shortening read operations in..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for shortening read operations in... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3216886