Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2007-09-18
2007-09-18
Patel, Rajnikant B. (Department: 2838)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S086000, C365S189050, C323S272000
Reexamination Certificate
active
11070347
ABSTRACT:
An integrated circuit includes at least a first and second compensation circuit that compensate for process, temperature, and other variable conditions that affect circuit performance. A compensation select circuit is coupled to selectively enable each of the first and second compensation circuits at respective first and second time periods to control a voltage on the input/output terminal to substantially equal a reference voltage and thereby determine appropriate compensation setting.
REFERENCES:
patent: 5805505 (1998-09-01), Zheng et al.
patent: 6249153 (2001-06-01), Moraveji
patent: 6265859 (2001-07-01), Datar et al.
patent: 6424131 (2002-07-01), Yamamoto et al.
patent: 6483793 (2002-11-01), Kim
patent: 6812732 (2004-11-01), Bui
patent: 6979984 (2005-12-01), Perrier et al.
Kumar Rohit
La Fetra Ross Voigt
Vishwanthaiah Sai V.
Patel Rajnikant B.
Zagorin O'Brien Graham LLP
LandOfFree
Method and apparatus for sharing an input/output terminal by... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for sharing an input/output terminal by..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for sharing an input/output terminal by... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3796978