Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-05-12
1999-07-27
Cabeca, John W.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
711141, 711166, 395586, 395392, 39575004, G06F 1200
Patent
active
059308214
ABSTRACT:
An apparatus and method for sharing cache lines within a split data/code cache is provided. The invention utilizes cache snoop and state control, coupled to both a data cache and a code cache, which allows the data cache to snoop fetches to the code cache, and allows the code cache to snoop reads and writes to the data cache. In addition, cache snoop and state control modifies the state of a particular cache line within both of the caches according to the MESI cache coherency protocol to allow a single cache line to reside in both the data cache, and the code cache, in a Shared state. The invention allows the shared cache line to be fetched from the code cache, and retrieved from the data cache, until it is overwritten or modified in the data cache. In one embodiment, an instance of a cache line within either the code or data cache can be snarfed into the other cache, and marked as shared.
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Gaskins Darius
Henry G. Glenn
Cabeca John W.
Huffman James W.
Integrated Device Technology Inc.
Moazzami Nasser
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