Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis
Reexamination Certificate
2007-08-24
2010-12-21
Suryawanshi, Suresh K (Department: 2115)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
C713S401000
Reexamination Certificate
active
07856570
ABSTRACT:
A method and system for shaping an electronic pulse with a two-pulse response. An input node receives an initial electronic pulse and splits the electronic pulse into a first path and a second path. An output node combines together the first path and the second path into an output path, and transmits a shaped electronic pulse, matched to an output impedance. An Ethernet chip generates two pulses and transmits the pulses along a first path and a second path respectively. A power combiner/splitter combines together the pulses along the first path and the second path into an output path, and transmits a shaped electronic pulse, matched to an output impedance.
REFERENCES:
patent: 5128627 (1992-07-01), Wendt
patent: 6853691 (2005-02-01), Kim
patent: 6956989 (2005-10-01), Van Tuyl
patent: 7012477 (2006-03-01), Harron et al.
patent: 7068881 (2006-06-01), Yoo
patent: 7212580 (2007-05-01), Hietala et
patent: 7245805 (2007-07-01), Alfano et al.
Liaw Haw-Jyh
Verma Shwetabh
NetLogic Microsystems, Inc.
Stattler-Suh PC
Suryawanshi Suresh K
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