Static information storage and retrieval – Read/write circuit
Patent
1990-10-23
1993-01-12
Popek, Joseph A.
Static information storage and retrieval
Read/write circuit
365201, G11C 700
Patent
active
051795345
ABSTRACT:
An IC having a test grid structure including intersecting probe lines and control/sense lines is used to apply desired logic states directly to internal transmission paths of select storage elements. A switch is located at each intersection for conducting the desired logic state to the internal transmission path. To achieve overwriting and storage of the desired logic state, the conventional storage element is modified to include a transmission gate activated by an overwrite enable signal. The overwrite enable signal is defined by one or more probe lines. To overwrite the contents of a storage element, the storage element is selected by turning on the switch with a probe line coupled to such switch, while the included transmission gate is disabled by receiving the overwrite enable signal. The logic state of the control/sense line is conducted into the storage element to the included transmission gate where it overwrites the current contents and is stored.
REFERENCES:
patent: 3761675 (1973-09-01), Mason et al.
patent: 3795859 (1974-03-01), Benante et al.
patent: 3806891 (1974-04-01), Eichelberger et al.
patent: 4293919 (1981-10-01), Dasgupta et al.
patent: 4513418 (1985-04-01), Bardell, Jr. et al.
patent: 4517672 (1985-05-01), Pfleiderer et al.
patent: 4613970 (1986-09-01), Masuda et al.
patent: 4749947 (1988-06-01), Gheewala
"Design for Testability-A Survey", by T. W. Williams, et al., Proceedings IEEE, vol. 71, pp. 359-416, Jan. 1983.
"A Logic Design Structure for LSI Testability", Eichelberger, et al., Proceedings 14th Design Automation Conf., Jun. 1977.
"Built-in Self-Test Techniques" by E. J. McClusky, IEEE Design and Test, vol. 2, No. 2, pp. 21-28, Apr. 1985.
"Built-in Self-Test Structures" by E. J. McClusky, IEEE Design and Test, vol. 2, No. 2, pp. 29-36, Apr. 1985.
"Voltage Checking Device" by G. Canard and A. Potocki, IBM Technical Disclosure Bulletin, vol. 8, No. 5, Oct. 1965.
Ferry Thomas V.
Pierce Kerry M.
Cross-Check Technology, Inc.
Popek Joseph A.
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