Electrical computers and digital data processing systems: input/ – Input/output data processing – Input/output access regulation
Reexamination Certificate
1998-07-30
2001-04-10
Beausoleil, Robert (Department: 2181)
Electrical computers and digital data processing systems: input/
Input/output data processing
Input/output access regulation
C710S060000, C710S033000, C710S034000, C710S058000, C709S233000
Reexamination Certificate
active
06216182
ABSTRACT:
FIELD OF THE INVENTION
The present invention is related to interrupt signals to alert a host that data packets are waiting for service. More specifically, the present invention is related to interrupt signals which are produced based on the speed the host can process data to alert a host that data packets are waiting for service.
BACKGROUND OF THE INVENTION
Data packets arriving from a network are usually placed into a buffer queue to be processed by a host computer. When and how often an interrupt signal needs to be generated to alert the host that there are data packets waiting in the queue is usually a compromise between latency (how long the data must wait in the queue before the host is notified) and performance (how often the host is interrupted—an interrupt can require considerable processing by the host). The existing technique of generating an interrupt for every data packet provides minimum latency but can overwhelm a slow host with a large number of interrupts.
Existing schemes generate an interrupt every packet. The card would generate an interrupt every time an end-of-packet buffer is enqueued to the host. This method provides minimum latency but can generate multiple interrupts per packet. Lots of interrupts can be generated for short packets and a slow host (worst combination).
Other existing methods use a counter or timer to limit the number of interrupts but can have latency problems especially for video or voice data. An interrupt is generated every N packet and M clock ticks from the time the last packet was enqueued. This method attempts to minimize the number of interrupt by generating an interrupt after N packets are enqueued (N is programmable). To minimize latence in case N is large, an interrupt is generated based on a timer. The timer is triggered at the end of a packet. If the timer crosses a M threshold (programmable) without detecting the end of another packet, then an interrupt is generated. Using this scheme requires the programming of two parameters: N and M. It is difficult for the host to determine the optimum value for N and M for different load conditions and variations of the host and card.
The present invention produces interrupt signals based on the speed the host can process data. The interrupt signals are sent at intervals which do not overwhelm the host and significantly effect performance.
SUMMARY OF THE INVENTION
The present invention pertains to a system for storing data. The system comprises a host for processing the data. The system comprises a buffer mechanism for storing data and producing interrupt signals to the host for informing the host there is data in the buffer mechanism for the host to process. The buffer mechanism adapting the production of interrupts based on the speed the host can process data. The host is in contact with the buffer mechanism.
The present invention pertains to a method for serving data. The method comprises the steps of storing data in a buffer mechanism. Then there is the step of sending an initial interrupt signal to a host from the buffer mechanism informing the host there is data in the buffer mechanism for the host to process. Next there is the step of transferring data in the buffer mechanism to the host. Then there is the step of processing data from the buffer mechanism with the host. Next there is the step of adapting when a subsequent interrupt signal is sent to the host based on the speed the host can process data. Then there is the step of sending the subsequent interrupt signal to the host from the buffer mechanism when there is data in the buffer mechanism for the host to process.
REFERENCES:
patent: 5068784 (1991-11-01), Kishino et al.
patent: 5586294 (1996-12-01), Goodwin et al.
patent: 5630111 (1997-05-01), Yoshida
patent: 5732285 (1998-03-01), Harrison et al.
patent: 5740467 (1998-04-01), Chmielecki, Jr. et al.
patent: 5758191 (1998-05-01), Kasebayashi et al.
patent: 5778218 (1998-07-01), Gulick
patent: 5802153 (1998-09-01), Sridhar et al.
patent: 5809337 (1998-09-01), Hannah et al.
patent: 5809338 (1998-09-01), Klein
patent: 5815677 (1998-09-01), Goodrum
patent: 5842044 (1998-11-01), No
patent: 5941962 (1999-08-01), Hirano
patent: 5978868 (1999-11-01), Maas
patent: 5983293 (1999-11-01), Murakami
patent: 6138190 (2000-10-01), Nording
Benson Michael H.
Nguyen Nhiem
Schlick Steven J.
Totolos, Jr. George
Beausoleil Robert
FORE Systems, Inc.
Phan Raymond N
Schwartz Ansel M.
LandOfFree
Method and apparatus for serving data with adaptable interrupts does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for serving data with adaptable interrupts, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for serving data with adaptable interrupts will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2514573