Static information storage and retrieval – Read/write circuit – Including signal comparison
Reexamination Certificate
2001-07-12
2002-09-24
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including signal comparison
C365S185200, C365S185210, C365S189050, C365S207000
Reexamination Certificate
active
06456539
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a circuit and a method for self-tracking dynamic sensing of a memory cell having built-in margins, and more particularly to a circuit and a method for sensing a memory signal from a nonvolatile memory device of the floating gate storage cell type.
BACKGROUND OF THE INVENTION
Sensing circuits to detect a memory signal from a selected memory cell of a memory device, such as a nonvolatile memory cell device of the floating gate storage type, are well known in the art. Referring to
FIG. 1
, there is shown a block level diagram of such a sensing circuit. Such a circuit is disclosed in U.S. Pat. No. 5,386,158. As disclosed in the '158 Patent, a sensing circuit
10
receives a memory signal from a selected memory cell, such as memory cell
12
m from a memory cell array
12
. The signal is passed through a multiplexer
16
to a first voltage amplifier
20
and to a first current mirror
22
. At the same time, during the sensing operation, a reference cell or a “dummy” cell
14
, generates a reference signal which is supplied to a second voltage amplifier
24
, and to a second current mirror circuit
26
. The sense signal
104
, which is the output of the first current mirror circuit
22
, and the sense ref signal
102
, which is the output of the second current mirror circuit
26
are compared in a comparator
28
. If the current from the sense signal
104
(representing the current flow through the selected memory cell) is greater than the current from the sense ref signal
102
(representing the current flow from the dummy cell
14
), then the output of the comparator
28
, Sout, will be in one state. If the current from the sense signal
104
(representing the current flow through the selected memory cell) is less than the current from the sense ref signal
102
(representing the current flow from the dummy cell
14
), then the output of the comparator
28
, Sout, will be in a different state. The Sout signal is then supplied directly to the output buffer and is the output of the memory device.
Referring to
FIG. 2
, there is shown in detailed circuit diagram the circuit shown in
FIG. 1
, and as disclosed in U.S. Pat. No. 5,386,158.
Because the sensing mechanism disclosed in U.S. Pat. No. 5,386,158 is current sensing type, care must be taken to activate the comparator
28
at the appropriate time. If the comparator
28
were activated too soon, an erroneous reading may result because the dummy cell
14
and the selected memory cell
12
m have not reached a steady state of current flow. In the prior art, one way to insure that the sensing circuit
10
and the dummy cell
14
and the selected memory cell
12
m have reached a steady state is to impose a delay on the sensing circuit
10
before outputting the Sout signal from the memory device. However, such a delay unnecessarily decreases the performance of the read operation. Accordingly, the present invention provides a self-tracking dynamic scheme to ensure the sense data are valid prior to outputting sensed data from the memory device, with a minimum of delay.
SUMMARY OF THE INVENTION
In the present invention, a method of sensing a memory signal from a selected memory cell of a memory device is disclosed. A reference signal generated from the memory device is compared to a threshold signal to determine the operational status of the memory device. The memory signal is compared to the reference signal, and generates a sensed signal. The sensed signal is outputted in response to the comparison between the reference signal and the threshold signal.
The present invention also relates to an apparatus for generating an output signal from the memory device with said output signal being the state of the selected memory cell sensed.
REFERENCES:
patent: 5594691 (1997-01-01), Bashir
patent: 5703820 (1997-12-01), Kohno
patent: 2002/0021588 (2002-02-01), Homma
Hoang Loc B.
Nguyen Hung Q.
Nguyen Sang Thanh
Gray Cary Ware & Freidenrich LLP
Ho Hoai
Silicon Storage Technology, Inc.
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