Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-01-27
2004-04-06
Jones, Hugh (Department: 2123)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C703S013000, C703S014000, C703S015000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06718520
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to electronic design automation (EDA) systems used for designing integrated circuits. The invention is more particularly related to a method for selectively providing hierarchy to a circuit design during the integrated circuit design process.
2. Description of the Prior Art
The design process for all integrated circuits is composed of several discrete operations. Initially, the proposed functionality for a circuit is analyzed by one or more chip designers. These designers define the logical components of the circuit and their interactions by specifying the logic design using design capture tools. These design capture tools are commonly implemented in software executing on an engineering workstation, with well-known input devices being used to receive design information from the chip designer, and output devices, such as computer displays, being used to provide visual feedback of the design to the designer as it is being constructed. Such software is typically implemented as part of an electronic design automation (EDA) system.
More particularly, the design entry operation involves generating a description of the logic design to be implemented on the circuit chip in an appropriate machine-readable form. A common method for specifying the integrated circuit design is the use of hardware description languages (HDL). This method allows a circuit designer to specify the circuit at the register transfer level (also known as a “behavior description”). Using this method, the circuit is defined in small building blocks. The names of the building blocks are specified by the circuit designer. Thus, they usually have logical names with specific functional meaning.
Encoding the design in a hardware description language (HDL) is a major design entry technique used to specify modern integrated circuits. Hardware description languages are specifically developed to aid a designer in describing a circuit. These languages often contain specific functions and syntax to allow complex hardware structures to be described in a compact and efficient way.
After the behavioral description is entered, the circuit designer typically simulates and verifies that the behavioral description correctly models the desired function. This is often accomplished using a HDL logic simulator. The HDL logic simulator may read the behavioral description, or a compiled version thereof, and simulate the function thereof.
To direct the HDL logic simulator, the circuit designer typically prepares a set of HDL test vectors. The HDL test vectors typically include input test patterns and corresponding output test patterns. The input test patterns may be used to force selected input signals within the behavioral description to predetermined values. The corresponding output test patterns may include the expected simulated values on selected output signals within the behavioral description. It should be noted that both the input and output test patterns typically reference specific signal names within the behavioral description.
The HDL logic simulator may sequentially simulate the functionality of the behavioral description for each input test pattern and provide simulated output values. The simulated output values may be compared with the corresponding output test patterns. Any discrepancy may indicate an error in the behavioral description, which may be corrected by the circuit designer. If an error is found and corrected, the modified behavioral description may be re-simulate to verify that the modified behavioral description correctly implements the desired function.
Once the behavioral description of the integrated circuit has been initially verified, it is transformed into a detailed description (also known as a structural or gate-level description). This conversion process is called synthesis. The detailed description represents the equation-based behavioral description in the form of gate-level objects (components) and the connections (nets) between the objects. The detailed description is used for the remaining design processes.
It is often necessary to verify that the detailed description is correct and that the integrated circuit implements the function expected by the circuit designer and meets predetermined performance goals (e.g. timing). This verification is currently achieved by estimated timing and simulation software tools. This simulation step is similar to the HDL simulation step described above. If errors are found or the resulting functionality is unacceptable, the circuit designer may modify the behavioral description as needed, and the behavioral description may be re-simulated and re-synthesized to produce an updated detailed description.
After timing verifications and functional simulation has been completed on the detailed description, placement and routing of the design's components is performed. These steps involve allocating components of the design to locations on the integrated circuit die and interconnecting the components to form nets. In some cases, it is advantageous to manually place certain critical user-defined blocks or cells within the design. The manual placement of these objects is typically accomplished via a placement tool (e.g. floor-planning tool). Stand alone placement tools are available, but many place and route tools have at least a limited floor-planning or placement capability.
Many user-defined blocks have an outer boundary defined therefor. To increase the predictability of the automatic placement of cells within the circuit design, the auto-placement tool may be set to place all un-placed cells or blocks that are within or below a user-defined block within the outer boundary of the user-defined block. The outer boundary may be appropriately sized to accommodate the placement of all cells or blocks that are within and below the user-defined block in the design hierarchy. In this case, the hierarchy of the detailed description may effect the placement of selected objects within the circuit design.
In some cases, it may be desirable to change the hierarchy of the detailed description such that selected cells or blocks are placed within an outer boundary of a selected user-defined block. Typically, this is accomplished by adding or changing hierarchical statement in the behavioral description. The resulting modified behavioral description may then be re-synthesized to provide the desired hierarchy in the detailed description.
The behavioral description may be changed many times during the design process, and for a variety of reasons. Whenever the behavioral description is changed, at least some of the signal names in the behavioral description may change. This may be problematic, particularly since the HDL test vectors may reference specific signal names within the behavioral description. Thus, the HDL test vectors may have to be updated each time the behavioral description is changed to simulate the modified behavioral description. This can be a tedious and time consuming task.
SUMMARY OF THE INVENTION
The present invention overcomes many of the disadvantages of the prior art by providing a method and apparatus for selectively providing hierarchy to a circuit design. The present invention contemplates providing a number of hierarchical statements in a description of the circuit design, wherein the syntax of the hierarchical statements allows the hierarchical statements to be visible when providing a first representation of the circuit design and effectively invisible when providing a second representation of the circuit design.
In a preferred embodiment, the number of hierarchical statements are provided in a behavioral description of a circuit design. The behavioral description is then provided to both a HDL simulator and a logic synthesis tool. The HDL logic simulator effectively disregard the hierarchical statements, and thus does not provide the hierarchy to the simulation representation of the circuit design. In contrast, the logic synthesis tool interprets the hierarchical statem
Engh Michael K.
Lautzenheiser Ted G.
Merryman Kenneth E.
Johnson Charles A.
Jones Hugh
Nawrocki, Rooney & Sivertson PA
Starr Mark T.
Unisys Corporation
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