Electronic digital logic circuitry – Function of and – or – nand – nor – or not – Field-effect transistor
Reexamination Certificate
1999-10-04
2001-05-15
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Function of and, or, nand, nor, or not
Field-effect transistor
C326S016000, C326S121000
Reexamination Certificate
active
06232799
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and apparatus for selectively controlling weak feedback in regenerative pass gate logic circuits.
DESCRIPTION OF THE RELATED ART
Pass gate static logic differs from traditional static logic by applying logical signals to transistor source, drain and gate terminals where static logic applies logic signals to only gate terminals. Pass gate logic as a family of circuit design styles offers significant advantages over static logic, particularly in performance and reduced area required. Therefore, it is desirable to use pass gate logic to implement as much of the logical function of a VLSI chip design as possible. A custom processor may incorporate a hundred thousand or more pass gate logic gates in its design.
One style of pass gate logic is the regenerative pass gate logic, (RPGL).
FIG. 1
shows a typical RPGL gate. True and complementary signals A and A_L drive the source of the pass gate transistors and B and B_L control the gates of the pass gate transistors to determine the state of nodes XNOR and XOR.
A problem with non-regenerative pass gate logic circuits is that the NFET pass gates will only drive node X (or X_L) to within a NFET threshold voltage of the supply (Vdd-Vt). Since node X is not driven completely to Vdd in non-RGPL circuits the PFET of the output inverter remains weakly on, allowing power dissipation.
Another common problem for pass gate logic is noise on the signals controlling gates (B and B_L in the example). Noise on these signals can allow the NFET pass gates to conduct partially. In
FIG. 1
, if A and B are at gnd and A_L and B_L are at Vdd, only one NFET, N
1
, is driving node X_L high. If noise on B and became high enough, N
3
would conduct a low signal and cause a noise glitch on node X_L. Additional power would also be dissipated since current flows from A_L through N
1
and N
3
to ground while noise is present on the gate of N
3
.
In SOI technology, pass gate logic is susceptible to higher bipolar current problem than in bulk technologies.
FIG. 4
shows a typical RGPL circuit which can be susceptible to bipolar current in SOI. If D
0
, D
1
, D
2
, and D
3
are all low (D
0
_L, D
1
_L, and D
3
_L are all high), and S
0
is high and S
1
, S
2
, S
3
are all low, node X will be low and node X_L will be high. The bodies of transistors N
4
, N
5
, N
6
, and N
7
will all leak to a high level. If the selects (S
0
-S
3
) remain as they were but D
1
, D
2
, and D
3
go high, D
1
_L, D
2
_L, and D
3
_L will go low. This will cause N
5
, N
6
, and N
7
to conduct parasitic bipolar current from node X_L to the inputs D
1
_L, D
2
_L, and D
3
_L. If the magnitude of this current is high enough, X_L will drop and a glitch will appear on the output OUT_L. Eventually N
4
will win and drive node X_L high but the noise form this bipolar affect will require a longer time to evaluate the proper values. This longer time may not be available for critical paths so incorrect logic operation is possible. This noise effect is greater as the number of pass gates are added to drive nodes X and X_L. The number of pass gates can be reduced but the cost would be more logic levels to provide the same function so timing would still be compromised.
RGPL attempts to solve the noise and power problems with the addition of two PFET feedback devices P
0
and P
1
. Since X and X_L will always be the complements of each other, each can be used to gate the feedback PFET of the other. This allows nodes X (or X_L) to increase from Vdd-Vt to Vdd when X_L (or X) goes low. However, the addition of the PFET feedback devices can result in a delay penalty since the first node to switch (X or X_L) must wait for the input drivers driving through the pass gates to defeat the PFET feedback device. If the PFET feedback device is too large this delay can be significant, and may even prevent the circuit from switching at all. If the PFET feedback device is sized too small it will not adequately address the noise and power issues described above.
Another style of pass gate logic is the N-channel pass gate logic, (NPGL).
FIG. 6
shows a typical NPGL gate. Data inputs, IN(O:n), are buffered with an inverter and Control inputs, Select (O:n), drive the NFET gates to determine the state of node X. A problem with the NPGL family is the NFETs pass gates will only drive node X to Vdd-Vt. Since node X is not driven completely to Vdd, the PFET of the output inverter remains weakly on allowing power dissipation. To solve this power problem a feedback device, P
0
, is added to bring node X from Vdd-Vt to Vdd when the circuit output OUT, falls from Vdd.
Another common problem for pass gate logic is noise on the Select(0:n) signals. Any noise will allow the pass gates to conduct partially. In
FIG. 6
, if IN(0:n-1) and Select(1:n) are at ground and Select(0) and IN(n) are at Vdd, only on NFET, NO, is driving node X high. If Select(n) had noise and became higher than ground, Nn would conduct a low signal to and cause a noise glitch on node X. Power would also be used while IN(0) is driving high and IN(n) is partially driving low. Pass gate logic is also victim to input noise from IN(0:n). The inverters help prevent noise problems but could still be seen by the node X if the relevant pass gate is on.
In SOI technology, pass gate logic is susceptible to higher bipolar current problem than in bulk technologies.
FIG. 6
shows a typical pass gate logic circuit. If IN(0:n) and Select(1:n) are at ground and Select (0) is at Vdd, only one NFET, N
0
, is driving node X high. If during this time in SOI technology the data inputs IN(1:n) switch from low to high, bipolar current will be introduced in NFETs N
2
through Nn pulling charge from node X. This bipolar current will drop node X's voltage while P
0
and N
0
devices continue to drive node X high. Eventually N
0
and P
0
will win and drive node X high but the noise from this bipolar affect will require a longer time to evaluate the proper values. This longer time may not be available for critical paths so incorrect logic operation is possible. This noise effect is greater as the number of pass gates are added to drive node X. The number of pass gates can be reduced but the cost would be more logic levels to provide the same function so timing would still be compromised.
Similar problems occur on Complementary Pass Gate Logic (CPL), illustrated in FIG.
7
.
The designer of a pass gate circuit must trade-off the performance impact of fewer or smaller pass gate devices connected to a nodes X and X_L versus the risk of not operating properly due to bipolar currents. Moreover, different environmental conditions dictate that a designer design for the worst-case situation. For example, for reliability reasons circuits are subject to higher voltages and temperatures than in which they are normally required to operate, such as, during burn-in, dynamic voltage stress, and the like, in order to stress the design and accelerate early failures. Typically reliability stressing is performed at a higher temperature and voltage but the performance requirements are much less. The circuits are required to be functional but need only perform at a fraction of the normal speed.
Since higher temperatures and voltages can aggravate leakage and noise mechanisms, the designer must design-in a greater amount of feedback than is required for normal operation to ensure that the circuits remain functional under the most severe conditions. This affects performance, not only under stress conditions where high performance is not required, but also under normal operation when performance is paramount.
Therefore, it is desired to have some method for providing more feedback when more is needed and performance is not a concern, for example, under reliability stress conditions, and providing less feedback when less is needed to maintain function and less is desirable for performance reasons.
SUMMARY OF THE INVENTION
A principal object of the present invention is to provide a method and apparatus for selectively controlling weak feedb
Allen David Howard
Stasiak Daniel Lawrence
International Business Machines - Corporation
Le Don Phu
Pennington Joan
Tokar Michael
LandOfFree
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