Electrical computers and digital processing systems: processing – Processing control – Arithmetic operation instruction processing
Reexamination Certificate
1999-07-20
2002-01-15
Coleman, Eric (Department: 2183)
Electrical computers and digital processing systems: processing
Processing control
Arithmetic operation instruction processing
C711S165000
Reexamination Certificate
active
06339823
ABSTRACT:
BACKGROUND OF THE INVENTION
The Intel Architecture™ (IA) originally provided integer instructions that operate on a set of integer registers referred to collectively as an integer register file. Early IA processors were complemented by external floating point processors, such as the 80287™ and 80387™ processors, which execute floating point instructions. These floating point processors included their own floating point register file, also referred to as the floating point register stack due to the manner in which floating point instructions reference individual registers within the floating point (FP) register file. In particular, the x87 architecture includes 8×80-bit floating point registers, comprising a 64-bit mantissa and a 16-bit characteristic (exponent). With the advent of the 80486™, the floating point unit was integrated into the processor itself along with the floating point register file.
Finally, the Pentium™ provided media enhancement technology, otherwise known as MMX instructions. These instructions provide enhanced performance for operations typically performed in multimedia applications, such as video and audio calculations. The MMX instructions operate on an 8×64-bit MMX register. However, for compatibility reasons discussed below, the 8 MMX registers are mapped, or aliased, onto the 8 floating point registers
506
, as shown in FIG.
5
. That is, from a programming perspective, the floating point and MMX register files comprise the same registers. Thus, a write of a value by an MMX instruction to register MM
6
followed by a read by a floating point instruction of register FP
6
would yield the value written by the MMX instruction.
The main reason for the design decision not to provide an architecturally separate MMX register file was to maintain compatibility with existing IA architecture operating systems, such as UNIX™, OS/2™ or Windows™. When performing task switches, these operating systems must save the state of the processor, which includes saving to memory the contents of both the integer and floating point register files. The addition of an architecturally distinct MMX register file would require a hugely expensive modification of already existing operating systems and application programs.
One result of the evolution of the IA described above is that programmers have developed certain conventions that they follow when developing software applications that employ floating point or MMX instructions. One convention is to mix floating point and MMX instructions only at the module or procedure level and to avoid mixing them at the instruction level. That is, programmers typically will code an entire procedure or module using only MMX (and integer instructions) without floating point instructions, or vice versa, rather than mixing MMX and floating point instructions in the same procedure. A switch from a floating point to an MMX instruction, or vice versa, is referred to as an instruction boundary event. Each transition between an FP instruction and an MMX instruction costs about 50 clocks. Thus, applications programmers typically attempt to minimize the number of instruction boundaries in their software applications.
A second convention is to leave all the floating point registers empty at the end of a section of floating point code (i.e., the tag bits of the floating point registers indicate they are empty), such as at the end of a floating point procedure. A third convention is similar to the second: leaving all the MMX registers empty at the end of an MMX procedure. The third convention is typically accomplished via the EMMS (empty multimedia state) instruction.
FIG. 6
shows a sample segment of source code illustrating two instruction boundary events. For example, execution of the instruction at L
62
constitutes an instruction boundary event since the previous instruction FLDZ is a floating point instruction. Moreover, execution of the instruction at L
66
constitutes an instruction boundary since only MMX- and FP-type instructions are considered; here, the ADD instruction at L
65
is an integer-type instruction and so is not considered. Therefore, since the last MMX or FP instruction that executed prior to the FINIT instruction was EMMS, i.e., an MMX instruction, an instruction boundary exists at L
66
.
As discussed previously, the MMX and floating point units of an IA microprocessor share the same physical register file. However, connecting both a floating point unit
502
and an MMX unit
504
to floating point register file
506
, as shown in
FIG. 5
, is costly in terms of wiring within a microprocessor, requiring additional metal layers to accomplish the necessary routing. Consider for example that
240
lines for data alone are required to interface the FP unit to the register file, two incoming 80-bit operand data buses and one outgoing 80-bit data bus. At least another 192 lines are needed to interface the MMX unit to the register file, two incoming 64-bit operand data buses and one outgoing 64-bit data bus. Add to this various control lines between the FP and MMX units and the register file. It is clear that the design of the FP and MMX hardware can quickly become a routing nightmare for the layout designer.
There is a need therefore for an architecture which can avoid the necessity of high density routing of signals on the computer chip when implementing the MMX technology. It is desirable to provide an architecture which provides fast transitions during the occurrence of an instruction boundary event.
SUMMARY OF THE INVENTION
In accordance with the invention a computing device includes a dual-register file architecture and a method for ensuring data coherency between an FP register file and an MMX register file includes monitoring write access to registers in the active register file and storing data indicative of which registers have been written to. Instructions to be executed are continually monitored for the occurrence of an instruction boundary event. Upon the occurrence of such event, control logic initiates an action to copy the registers in a first of the register files (i.e., the active register file) over to corresponding registers in a second of the register files, namely the receiving register file. Write-enable logic associated with each of the registers of the second register file is disabled based on the stored data for those registers in the first register file which have not been written to. Thus, an attempt to write into a write-disabled register will fail and thus preserve its original contents. This facilitates the control logic by obviating the need to make an extra check to determine whether a register should be copied or not. By disabling the appropriate registers, protection against unintended overwrites is automatically provided and only those registers which need to be overwritten to achieve coherence will be affected.
Circuitry in accordance with the invention includes an instruction decoder configured to detect MMX- and FP-type instructions. A data store is used to store the last MMX- or FP-type instruction that was decoded. Write detection logic monitors the occurrence of a write operation to a register, and a status register contains information as to which of the registers have been written to. The status register is coupled to write-enable logic associated with each register. The decoder detects when a currently executing MMX- or FP-type instruction differs from that indicated in the data store and asserts a signal indicating the occurrence of an instruction boundary event. The signal activates control logic to cause a transfer of data from one register file to the other in order to attain coherency between the two register files. The control logic generates signals which are coupled to the write-enable logic of the data-receiving registers. These signals along with the status register determine whether write operations to the receiving registers will succeed. Consequently, the control logic does not need to determine whether a transferring register was written to prior to moving the data ov
Coleman Eric
Yee George B. F.
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