Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Reexamination Certificate
2011-03-29
2011-03-29
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
C326S095000, C326S021000, C365S154000
Reexamination Certificate
active
07915924
ABSTRACT:
A system and method to operate an electronic device, such as a memory chip, with an output driver circuit that is configured to include an ODT (On-Die Termination) mode detector detects whether there is sufficient internal clocking available to operate the ODT portion in the output driver in the synchronous mode of operation or to switch the operation to the asynchronous mode. The clock-sufficiency based determination of internal ODT mode of operation (synchronous vs. asynchronous) avoids utilization of complex and inflexible clock processing logic in an ODT control unit in the output driver. This enables the actual clocking to the ODT circuitry to be changed during various device operational modes (e.g., active, power down, etc.) without re-designing the ODT control logic for each of those modes. The simplicity and flexibility of the ODT mode detector design allows for efficient use of chip real estate without affecting the signal transfer speed of the output driver in the electronic device. Because of the rules governing abstracts, this abstract should not be used to construe the claims.
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Cho James H.
Dorsey & Whitney LLP
Lo Christopher
Micro)n Technology, Inc.
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