Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1995-07-07
1998-07-07
Chan, Eddie P.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
G06F 1208
Patent
active
057784272
ABSTRACT:
The present invention provides a cache manager (CM) for use with an address translation table (ATT) which take advantage of way information, available when a cache line is first cached, for efficiently accessing a multi-way cache of a computer system having a main memory and one or more processors. The main memory and the ATT are page-oriented while the cache is organized using cache lines. The cache includes a plurality of cache lines divided into a number of segments corresponding to the number of "ways". Each cache line includes an address tag (AT) field and a data field. The way information is stored in the ATT for later cache access. In this implementation, "waylets" provide an efficiency mechanism for storing the way information whenever a cache line is cached. Accordingly, each table entry of the ATT includes a virtual address (VA) field, a physical address (PA) field, and a plurality of waylets associated with each pair of VA and PA fields. Subsequently, the waylets can be used to quickly index directly into a single segment of the cache as follows. Upon receiving a virtual address of a target cache line, the CM attempts to match a virtual address field of one of the ATT entries with a page index portion of the virtual address. If there is a match, a waylet of the ATT entry is retrieved using a page offset portion of the virtual address. If the waylet value is valid, the CM indexes directly into a single cache line using the waylet value, the physical address field of the ATT entry and the page offset portion of the virtual address. If the AT field of the retrieved cache line matches with a portion of the physical address field of the ATT entry, the processor retrieves the data field of the cache line using the page offset portion of the VA. If the AT field does not match, the target cache line is retrieved from the main memory, and the waylet value in both the ATT and the main memory is updated.
REFERENCES:
patent: 5055999 (1991-10-01), Frank et al.
patent: 5235697 (1993-08-01), Steely, Jr.
patent: 5297265 (1994-03-01), Frank et al.
patent: 5341483 (1994-08-01), Frank et al.
patent: 5369753 (1994-11-01), Tipley
patent: 5418922 (1995-05-01), Liu
patent: 5640532 (1997-06-01), Thome et al.
"Computer Architecture A Quantitative Approach", by John L. Hennessy and David A. Patterson, Chapter 8, pp. 403-490, QA76.9A73P377, 1990.
"Decoupled Sector Caches: conciliating low tag implementation cost and low miss ratio", by Andre Seznec, IRISA, Campus de Beaulieu, France, 21th International Symposium on Computer Architecture, Apr. 1994. (11 pages).
"Cache Memories", by Alan Jay Smith, University of California, Berkeley, Computing Surveys, vol. 14, No. 3, Sep. 1982, pp. 474-530, 1982 ACM 0010-4892/82/0900-0473.
"Cache Design of A Sub-Micron CMOS System/370", J.H. Chang, H. Chao, and K.So, IBM T.J. Watson Research, 1987 ACM0084-7495/87/0600-0208, pp. 208-213.
"A Case for Direct-Mapped Caches", by Mark D. Hill, University of Wisconsin, IEEE Computer vol. 21, No. 12, Dec. 1988, pp. 25-40.
Hagersten, Erik, "Simple COMA Node Implementations," HICSS, Jan. 1994, pp. 1-12.
Hagersten Erik
Singhal Ashok
Chan Eddie P.
Kivlin B. Noel
Sun Microsystems Inc.
Verbrugge Kevin
LandOfFree
Method and apparatus for selecting a way of a multi-way associat does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for selecting a way of a multi-way associat, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for selecting a way of a multi-way associat will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1218550