Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Encapsulating
Reexamination Certificate
2000-02-01
2001-04-10
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Encapsulating
C438S125000
Reexamination Certificate
active
06214650
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to electronic packaging assemblies, and more particularly, to ball grid array packages that are surface mounted on printed wiring boards.
BACKGROUND OF THE INVENTION
Electronic package assemblies which utilize various substrates (e.g. printed wiring boards comprised of conductive structures in epoxy resin or the like material) having one or more electronic packages surface mounted thereon are known. Typically, such electronic package assemblies include a relatively flat housing component having therein at least one semiconductor device, which semiconductor device is in turn electrically connected to various conductive leads which project from designated sides of the housing component. One such example is known in the art as a “flat pack.” Electronic package assemblies provide various functions (e.g. memory, logic) for the overall system which utilizes package assemblies of this type.
Typically, the conductive leads which project from electronic package assemblies are electrically coupled to respective conductive pads that form the circuitry on an upper surface of a printed wiring board. As is known, various solder compositions may be used to provide individual electrical interconnections between respective pairs of leads and conductors.
In high reliability applications where high levels of humidity can be present (e.g. aircraft flight management computers), these electrical interconnections must be protected from the harmful effects of moisture (e.g. corrosion caused by condensation). Also, these interconnections must be protected from shorting out by the potential presence of loose foreign conductive particles. In the current art, various organic coatings (e.g. epoxy, acrylic, paraxylylene) are applied as a thin, continuous film to the leads, solder and conductive pads by various techniques (e.g. spray, dip, vapor deposition) so as to provide a barrier to moisture and foreign conductive particles.
Recently, electronic package assemblies have been developed which use small solder balls (typically 0.025 inches in diameter) instead of leads to provide an electrical interconnection between the package and the circuit board. These solder balls are arranged in an array (typically 0.050 inch on center) under the electronic package housing. Such packages are referred to in the art as “ball grid arrays” (BGAs). BGA devices, having many more interconnections than a leaded electronic package with the same housing dimensions, allow for greater input/output capability. BGA devices also eliminate the need to route package leads to the outer edges of the electronic package. Finally, BGA devices provide shorter interconnect lengths which result in improved electrical performance. The advantages described above, along with the low cost of ball grid array packaging, make BGA devices an ideal packaging format for many integrated circuit applications. Furthermore, these BGA devices are capable of being surface mounted to the substrate's respective circuitry (e.g. conductive pads) using known techniques, e.g. soldering.
When using a spray technique to apply coatings (e.g. epoxy, acrylic) to printed wiring board assemblies which have BGA devices mounted thereon, most of the BGA solder balls are left uncoated due to shadowing effects of the housing. Also, some coating material can fill or bridge the gap between the housing and the printed wring board while some solder balls are left partially coated. “Coating bridges” and partially coated solder balls can also occur when using a dip technique to apply coatings due to the small gap between the housing and the printed wiring board combined with the large housing length and width. It has been discovered than when solder balls are partially coated or coating bridges are present, relatively significant stress is placed on the solder ball interconnection. The stress can adversely effect such interconnections, possibly causing separation of the interconnection. Such resulting separation in turn may cause disconnection between the solder ball and the printed wiring board, possibly rendering the package partially inoperative. Such stress is caused during operation of the package as a result of relatively substantial difference in the coefficient of thermal expansion of the solder and the coefficient of thermal expansion of the coating.
One method of coating BGA solder balls that could provide a thin, continuous and uniform coating on all solder balls without filling or bridging the gap between the housing and the printed wiring board is to apply paraxylylene (e.g. Parylene D from Union Carbide Corporation) using a vapor deposition process.
The cost of performing this process however, can be relatively high, requiring complex and expensive equipment. Also, paraxylylene coatings are very difficult to repair.
It is therefore an object of this invention to enhance the electronic package assembly art.
It is another object of this invention to provide a method and apparatus for sealing a BGA and printed wiring board interconnection against the effects of moisture and foreign conductive particles which obviates the aforementioned thermal stress problem.
It is a further object of the invention to provide such a method which can be performed at a relatively low cost.
SUMMARY OF THE INVENTION
The objects set forth above as well as further and other objects and advantages of the present invention are achieved by the embodiments of the invention described hereinbelow.
The present invention provides an electronic package assembly in which a ball grid array (BGA) is surface mounted to a printed wiring board using solder balls. Tubing is placed along the perimeter of the BGA housing to prevent subsequently applied sealant from contacting the solder balls or filling the gap between the BGA housing and the printed wiring board. The method of this invention includes the steps necessary to effect such a sealer being incorporated within the electronic package assembly. This results in a seal that prevents electrical disconnection in the solder joint during operation of the electronic package assembly.
The present invention together with the above and other advantages may best be understood from the following detailed description of the embodiments of the invention illustrated in the drawings, wherein:
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patent: 5650593 (1997-07-01), McMillan et al.
patent: 5834339 (1998-11-01), Distefano et al.
patent: 6107123 (2000-08-01), Distefano et al.
patent: 54-161271 (1979-12-01), None
patent: 56-158460 (1981-12-01), None
Felice John B.
Nagerl Andrew J.
Cohen Jerry
Erlich Jacob N.
Lee Calvin
Lockheed Martin Corporation
Perkins Smith & Cohen LLP
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