Electrical computers and digital data processing systems: input/ – Access arbitrating – Access prioritizing
Reexamination Certificate
2007-03-13
2007-03-13
Auve, Glenn A. (Department: 2111)
Electrical computers and digital data processing systems: input/
Access arbitrating
Access prioritizing
C710S045000, C710S117000, C370S395210, C370S395410, C370S395420
Reexamination Certificate
active
10963271
ABSTRACT:
The present invention is directed to a method and apparatus for scheduling a resource to meet quality of service guarantees. In one embodiment of three levels of priority, if a channel of a first priority level is within its bandwidth allocation, then a request is issued from that channel. If there are no requests in channels at the first priority level that are within the allocation, requests from channels at the second priority level that are within their bandwidth allocation are chosen. If there are no requests of this type, requests from channels at the third priority level or requests from channels at the first and second levels that are outside of their bandwidth allocation are issued. The system may be implemented using rate-based scheduling.
REFERENCES:
patent: 4688188 (1987-08-01), Washington
patent: 5107257 (1992-04-01), Fukuda
patent: 5218456 (1993-06-01), Stegbauer et al.
patent: 5265257 (1993-11-01), Simcoe et al.
patent: 5274769 (1993-12-01), Ishida
patent: 5287464 (1994-02-01), Kumar et al.
patent: 5363484 (1994-11-01), Desnoyers et al.
patent: 5379379 (1995-01-01), Schwartz et al.
patent: 5469473 (1995-11-01), McClear et al.
patent: 5530901 (1996-06-01), Nitta
patent: 5546546 (1996-08-01), Bell et al.
patent: 5557754 (1996-09-01), Stone et al.
patent: 5634006 (1997-05-01), Baugher et al.
patent: 5664153 (1997-09-01), Farrell
patent: 5673416 (1997-09-01), Chee et al.
patent: 5745913 (1998-04-01), Pattin et al.
patent: 5748629 (1998-05-01), Caldara et al.
patent: 5809538 (1998-09-01), Pollmann et al.
patent: 5917804 (1999-06-01), Shah et al.
patent: 5926649 (1999-07-01), Ma et al.
patent: 5948089 (1999-09-01), Wingard et al.
patent: 5982780 (1999-11-01), Bohm et al.
patent: 5996037 (1999-11-01), Emnett
patent: 6023720 (2000-02-01), Aref et al.
patent: 6092137 (2000-07-01), Huang et al.
patent: 6104690 (2000-08-01), Feldman et al.
patent: 6119183 (2000-09-01), Briel et al.
patent: 6122690 (2000-09-01), Nannetti et al.
patent: 6141713 (2000-10-01), Kang
patent: 6167445 (2000-12-01), Gai et al.
patent: 6199131 (2001-03-01), Melo et al.
patent: 6212611 (2001-04-01), Nizar et al.
patent: 6253269 (2001-06-01), Cranston et al.
patent: 6266718 (2001-07-01), Klein
patent: 6330225 (2001-12-01), Weber et al.
patent: 6335932 (2002-01-01), Kadambi et al.
patent: 6363445 (2002-03-01), Jeddeloh
patent: 6430156 (2002-08-01), Park et al.
patent: 6499090 (2002-12-01), Hill et al.
patent: 6510497 (2003-01-01), Strongin et al.
patent: 6530007 (2003-03-01), Olarig et al.
patent: 6578117 (2003-06-01), Weber
patent: 6628609 (2003-09-01), Chapman et al.
patent: 6636482 (2003-10-01), Cloonan et al.
patent: 6721325 (2004-04-01), Duckering et al.
patent: 6804738 (2004-10-01), Weber
patent: 6804757 (2004-10-01), Weber
patent: 6862265 (2005-03-01), Appala et al.
patent: 6961834 (2005-11-01), Weber
patent: 6976106 (2005-12-01), Tomlinson et al.
patent: 2001/0026535 (2001-10-01), Amou et al.
patent: 2002/0129173 (2002-09-01), Weber et al.
patent: 2002/0138687 (2002-09-01), Yang et al.
patent: 2002/0174227 (2002-11-01), Hartsell et al.
patent: 2003/0074504 (2003-04-01), Weber
patent: 2003/0074519 (2003-04-01), Weber
patent: 2003/0079080 (2003-04-01), DeMoney
patent: 02 70 7854 (2004-11-01), None
patent: 02 72 1116 (2006-05-01), None
patent: WO 00/29956 (2000-05-01), None
patent: WO 01/75620 (2001-10-01), None
Lamport, Leslie; “How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs”, IEEE Transactions on Computers, vol. C-28, No. 9, Sep. 1979, pp. 690-691.
Rixner, Scott et al., “Memory Access Scheduling”, to appear in ISCA-27 (2000), Computer Systems Laboratory, Stanford University, Stanford, CA 94305, pp. 1-11.
Search Report for PCT/US02/05438, mailed May 24, 2002, 1 page.
Search Report for PCT/US02/05288, mailed May 20, 2002, 1 page.
Search Report for PCT/US02/05439, mailed Jun. 26, 2002, 1 page.
Search Report for PCT/US02/05287, mailed Jul. 11, 2002, 1 page.
Rixner et al., “A Bandwidth-Efficient Architecture for Media Processing”, Micro-31, 1998, pp. 1-11.
Drew Wingard, “MicroNetworks-Based Integration for SOCs.” In Design Automation Conference, 2001, pp. 673-677, 5 pages.
Ron Ho, et al., “The Future of Wires”. In Proceedings of the IEEE, vol. 89, No. 4, pp. 490-504, Apr. 2001, 15 pages.
William J. Dally, et al., “Route Packets, Not Wires: On-Chip Interconnection Networks.” In Design Automation Conference, pp. 684-689, Jun. 2001, 6 pages.
Jim Kurose, “Open Issues and Challenges in Providing Quality of Service Guarantees in High-Speed Networks”, ACM Computer Communication Review, vol. 23, No. 1, pp. 6-15, Jan. 1993, 10 pages.
Hui Zhang, “Service Disciplines for Guaranteed Performance Service in Packet-Switching Networks”, Proceedings of the IEEE, vol. 83, No. 10, Oct. 1995, pp. 1374-1396, 23 pages.
Dimitrios Stiliadis, et al., “Latency-Rate Servers: A General Model for Analysis of Traffic Scheduling Algorithms”, In Proceedings of IEEE INFOCOM 96, Apr. 1996, pp. 111-119, 9 pages.
K. Lahiri, et al., “LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs”. In Proceedings of Design Automation Conference 2003, Las Vegas, Jun. 2001, pp. 15-20, 6 pages.
William J. Dally, “Virtual-channel Flow Control”, In Proceedings of the 17th Int. Symp. on Computer Architecture, ACM SIGARCH, May 1990, vol. 18, No. 2, pp. 60-68, 9 pages.
Drew Wingard, et al., “Integration Architecture for System-on-a-Chip Design”, In Proc. of the 1998 Custom Integrated Circuits Conference, May 1998, pp. 85-88, 4 pages.
Weber, Wolf-Dietrich, et al., “Enabling Reuse via an IP Core-centric Communications Protocol: Open Core Protocol”, In Proceedings of the IP 2000 System-on-Chip Conference Mar. 2000, pp. 1-5.
Ivo Adan and Jacques Resing, “Queueing Theory”, Eindoven University of Technology, Feb. 14, 2001, pp. 23-27.
PCT International Search Report for PCT/US2004/035863, Int'l filing Oct. 27, 2004, mailed Aug. 9, 2005, 9 pages.
Wingard, Drew, “Sonics SOC Integration Architecture,” Sonics, Inc., 1500 presentation, 1999, 25 pages, www.OCP-IP.org.
Kamas, Alan, “The SystemC OCP Models; An Overview of the SystemC Models for the Open Core Protocol,” NASCUG, 2004, 30 pages.
Wingard, Drew, “Socket-Based Design Using Decoupled Interconnects,” Sonics, Inc., 30 pages, downloaded Jun. 14, 2004, www.OCP-IP.org.
Haverinen, Anssi, “SystemC™ Based SoC Communication Modeling for the OCP Protocol,” White Paper, Oct. 2002, V1.0, 39 pages.
Wingard, Drew, “Tiles—An Architectural Abstraction for Platform-Based Design,” Perspective article 2, EDA Vision, Jun. 2002, 3 pages, www.edavision.com.
Weber, Wolf-Dietrich, “Efficient Shared DRAM Subsystems for SOCs,” Sonics, Inc., 2001, 6 pages.
“Open Core Protocol Specification,” OCP International Partnership, Release 1.0, 2001.
Wingard, Drew PhD., “Integrating Semiconductor IP Using μNetworks,” ASIC Design, Jul. 2000 electronic engineering, 3 pages.
Wingard, Drew, “Tiles: the Heterogeneous Processing Abstraction for MPSoC,” Sonics, Inc., Smart Interconnect IP, 2004, 35 pages, www.OCP-IP.org.
Chou, Joe, “System-Level Design Using OCP Based Transaction-Level Models,” presentation, Denali MemCom Taiwan 2005, OCP International Partnership, 23 pages.
Wingard, Drew, “A Non-Blocking Intelligent Interconnect for AMBA-Connected SoCs,” Sonics, Inc., CoWare Arm Developer's Conference, Oct. 6, 2005, 39 pages.
Weber, Wolf-Dietrich, et. al., “A Quality-of-Service Mechanism for Interconnection Networks In System-on-Chips,” 1530-1591/05, 2005 IEEE, 6 pages.
Casini, Phil, “Measuring the Value of Third Party Interconnects,” Sonics, Inc., White Paper, 2005, 11 pages, www.sonicsinc.com.
European Search Report for International Application No. EP 02 71 3653, mailed on May 29, 2006,
Auve Glenn A.
Blakely , Sokoloff, Taylor & Zafman LLP
Sonics, Inc.
LandOfFree
Method and apparatus for scheduling a resource to meet... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for scheduling a resource to meet..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for scheduling a resource to meet... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3733384