Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1999-12-30
2004-06-08
Frejd, Russell (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C716S030000, C716S030000
Reexamination Certificate
active
06748352
ABSTRACT:
BACKGROUND
1. Field
An embodiment of the present invention relates to the field of integrated circuit design and, more particularly, to the design of integrated circuits including scan cells.
2. Discussion of Related Art
A typical design process for an integrated circuit begins with architecture design followed by a logic design phase that produces a register transfer level (RTL) model of the integrated circuit and a circuit design phase that produces a switch level schematic. Once a switch level schematic is available, a formal verification (FV) process may be performed to verify that the schematic and the RTL model are functionally equivalent (verify the schematic against the RTL).
While an FV process may be used to verify the schematic against the RTL model for a normal operating mode of the integrated circuit, if scan cells are included in the design, there may be issues during scan operations that were not revealed during FV. Vectors shifted into scan cells through the scan chains included in the integrated circuit may cause contention that is not detected by the FV process, for example.
FIG. 1
shows an example of a portion
100
of an integrated circuit to be verified. The circuit
100
includes control lines
105
-
107
that act as select lines for the multiplexer (mux)
110
. The mux
110
receives input values on input lines
111
-
113
and provides an output at node
115
. In this example, during a normal mode of operation, the logic
120
is configured to ensure that only one of the select lines
105
-
107
is asserted at any one time. During this normal mode of operation, scan cells
126
-
128
coupled to outputs of the logic
120
act as simple latches that pass output values from the logic
120
through a scan cell fan-out cone
130
to the select lines
105
-
107
of the mux
110
.
By ensuring that only one of the select lines
105
-
107
is asserted at once, contention is avoided at the output node
115
in the case that different input values are received on the input lines
111
-
113
. Contention at the output node
115
creates a DC current path that can damage a chip that includes the integrated circuit
100
and/or compromise its reliability.
While contention at a mux output node
115
is described above, contention may also occur on a bus with a similar configuration (e.g. a tristate bus), for example, in a similar manner and may be even more problematic.
During an FV process to verify the circuit
100
, where FV is performed at sequential logic boundaries, the logic
120
does not control the values of the control signals
105
-
107
because there is a sequential boundary at the scan chain
125
. Thus, one or more FV properties may be specified at the inputs of the logic
130
to constrain the controlling signals
105
-
107
such that only one of the signals can be asserted at any one time. An example of such a property may be MUTEX (
105
,
106
,
107
) (where MUTEX indicates mutually exclusive).
When FV is performed on the circuit
100
using this FV property, contention is avoided at the output node
115
during the FV process.
An issue may arise, however, during scan testing, when test vectors are shifted into the scan chain and/or when they are applied to the signal lines
105
,
106
and
107
. During such testing, the logic
120
does not have control over the values of the signals applied to the signal lines
105
-
107
. Because any combination of values may be shifted into the scan cells
126
-
128
during scan testing, contention may be caused at the output node
115
either during a shift operation or as the vector shifted into the scan chain is otherwise applied to the signal lines
105
-
107
.
Currently, such sites where contention may occur during scan testing can be difficult to detect. One approach is to exhaustively simulate all possible test vectors that may be applied to each scan chain. Another approach is to inspect contention sites manually after an issue, such as wafer or circuit damage, has occurred. Such processes are time consuming, may require additional expertise, may be subject to human error and/or may happen late in the manufacturing cycle such that any design changes are expensive to make.
Where immediate damage to a chip does not occur as a result of contention, or the circumstances that cause the contention are relatively rare, some manufacturers may choose to ignore the issue. Quality or reliability of the integrated circuit chip may be compromised as a result.
Another approach is to design scan cells that do not cause contention. This may be done, for example, by avoiding the use of tristate elements. Such a design approach may, however, unacceptably compromise the speed of the integrated circuit. Alternatively, scan cells may be designed to hold their state such that contention issues are avoided during scan shift operations. Some scan cells designed in this manner may result in increased area and operation overhead.
REFERENCES:
patent: 4937827 (1990-06-01), Beck et al.
patent: 5068603 (1991-11-01), Mahoney
patent: 5541849 (1996-07-01), Rostoker et al.
patent: 5572437 (1996-11-01), Rostoker et al.
patent: 5646567 (1997-07-01), Felix
patent: 5847561 (1998-12-01), Whetsel
patent: 5943489 (1999-08-01), Shiratori
patent: 6170072 (2001-01-01), Moriguchi et al.
patent: 6247165 (2001-06-01), Wohl et al.
patent: 6295636 (2001-09-01), Dupenloup
patent: 6321186 (2001-11-01), Yuan et al.
patent: 6446230 (2002-09-01), Chung
Srinivinas, N.C.E.; Agrawal, V.D., “Formal verification of digital circuits using hybrid simulation,” IEEE Circuits and Devices Magazine , vol.: 4 Issue: 1 , Jan. 1988, pp. 19-27.*
Narendran, P.; Stillman, J., “Formal verification of the Sobel image processing chip,” Proceedings of the 25th ACM/IEEE Design Automation Conference, 1988, pp.: 211-217.*
Wohl, P.; Waicukauski, J., “Using ATPG for clock rules checking in complex scan designs,” The 15th IEEE VLSI Test Symposium, 1997, pp.: 130-136.*
Macil et al., E. Formal Verification of Digital Systems by Automatic Reduction of Data Paths, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, No. 10, Oct. 1997, pp. 1136-1156.*
Heitmeyer et al., C. Using Abstraction and Model Checking to Detect Safety Violations in Requirements Specifications, IEEE Transactions on Software Engineering, vol. 24, No. 11, Nov. 1998, pp. 927-948.*
Chau, S. Fault Injection Boundary Scan Design for Verification of Fault Tolerant Systems, IEEE, International Test Conference, 1994, pp. 677-682.
Maneparambil Kailasnath S.
Singh Puneet
Yuen Joel T.
Faatz Cynthia T.
Frejd Russell
Intel Corporation
LandOfFree
Method and apparatus for scan design using a formal... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for scan design using a formal..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for scan design using a formal... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3318774