Method and apparatus for sampling data from a memory

Details Method and apparatus for sampling data from a memory Method and apparatus for sampling data from a memory

1996-10-01

1999-01-12

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

711105, G06F 1206

Patent

active

058601287

ABSTRACT:
A novel method for performing memory accesses. Falling edges of a column address strobe (CAS) signal are used to cause dynamic random access memories (DRAMs) to drive data corresponding to the current address onto a data bus coupled to the input of a set of latches. A memory latch data (MLAD) signal is used to enable the set of latches. When the MLAD signal is asserted, the latches latch the data at the input in response to a falling edge of the CAS signal. When the MLAD signal is deasserted, the latch does not latch the data at the input in response to the falling edge of the CAS signal. Since the same signal (CAS) is used to control when the data is driven by the DRAMs and when the data is latched by the latches, the differences in output timings, signal path delays, and loads are avoided. The use of expensive timing compensation circuits and special tuning of these circuits for each circuit board redesign is thereby avoided.

REFERENCES:
patent: 5261068 (1993-11-01), Gaskins et al.
patent: 5465343 (1995-11-01), Henson et al.
patent: 5490114 (1996-02-01), Butler et al.

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