Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1997-05-22
1999-06-08
Tokar, Michael
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
326 95, 326 98, H03K 19096
Patent
active
059107359
ABSTRACT:
A dynamic logic circuit operates in a normal mode, and in a safe mode for which the circuit is less susceptible to noise than with the normal mode. The dynamic logic circuit includes a logic network having at least one input, a precharge device having a storage node connected to the logic network, and a device for varying a capacitance of the storage node to provide the normal and safe modes of operation. In one embodiment, the capacitance at the storage node is varied by selectively connecting the storage node to a capacitor, particularly to a DRAM cell capacitor. The DRAM cell is advantageously fabricated on a chip in close proximity to the storage node. A logic process using a plurality of such dynamic logic circuits can have means for independently operating each of the circuits in the safe mode, and the circuits can be monitored during the normal and safe operation modes to determine whether any are failing during the normal operation mode, e.g., due to excess noise.
REFERENCES:
patent: 4694205 (1987-09-01), Shu et al.
patent: 5065048 (1991-11-01), Asai et al.
patent: 5831451 (1998-11-01), Bosshart
Dillon Andrew J.
Duong Qui Van
International Business Machines - Corporation
Musgrove Jack V.
Tokar Michael
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