Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-02-14
2004-11-16
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06820248
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to routing for devices with different pitch, and more particularly to routing of a core embedded in a programmable logic device where the core comprises a different pitch than the programmable logic device.
BACKGROUND OF THE INVENTION
Programmable logic devices exist as a well-known type of integrated circuit that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic devices, called a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. The configuration bitstream may be read from an external memory, conventionally an external integrated circuit memory EEPROM, EPROM, PROM, and the like, though other types of memory may be used. The collective states of the individual memory cells then determine the function of the FPGA.
A recent development in FPGA technology involves providing FPGAs comprising a plurality of what are known as “standard cells.” These “standard cells” are provided inside an FPGA as functional blocks and have a set height. Notably, the term “standard cell” is not to imply that any standard, de facto or otherwise, exists, as standard cell size may vary from company to company. So, for example, logic blocks, such as a flip-flop, a NAND gate, and an inverter, among other well-known logic circuits, each will lay out with a same height, but may have different lengths. This height is conventionally dependent on pitch of a company's integrated circuit process for one or more interconnect or metal layers. A standard cell may be made up of several logic blocks, each with a same height, but possibly with different lengths. Thus, each standard cell will have a same height but may have varying lengths. Standard cells may be assembled for providing interconnectivity logic or “glue logic.” Thus, an FPGA may be connected to an embedded device to carry out complex tasks.
However, an embedded device or core may not have the same layout pitch as an FPGA. Moreover, FPGA exclusive routing over an embedded core further complicates routing to an embedded core. A placement and routing database used by a routing program creates routing for connecting an FPGA to an embedded core. However, non-equivalent pitch between such an FPGA and embedded core causes design rule violations. These design rule violations heretofore were addressed by manual re-routing. However, checking a design for such violations and manually re-routing can delay production by one or more months depending on complexity and number of connections between the FPGA and embedded core.
Accordingly, it would be desirable and useful to provide a layout rules for implementation in a placement and routing database that would reduce design rule violations owing to differences in pitch between an FPGA and an embedded core.
SUMMARY OF THE INVENTION
An aspect of the present invention is a method for configuring a routing program for routing connections between an integrated circuit device and an embedded core. More particularly, a first horizontal pitch and a first vertical pitch is obtained for one of the integrated circuit device and the embedded core, and a second horizontal pitch and a second vertical pitch is obtained for the other of the integrated circuit device and the embedded core, where the first vertical pitch and the second vertical pitch are not equal. A first connection layer input, including, but not limited to, the first vertical pitch and a horizontal direction, is provided to the routing program, and a second connection layer input, including, but not limited to, the second horizontal pitch and a vertical direction, is provided to the routing program.
An aspect of the present invention is an integrated circuit device comprising a first device coupled to a second device. The first device comprises a first horizontal pitch and a first vertical pitch. The second device comprises a second horizontal pitch and a second vertical pitch. At least one interconnect layer is for coupling the first device and the second device. The interconnect layer comprises a set of pitches selected from: (i) the first vertical pitch and the second horizontal pitch, and (ii) the first horizontal pitch and the second vertical pitch.
REFERENCES:
patent: 4758985 (1988-07-01), Carter
patent: 4855669 (1989-08-01), Mahoney
patent: 5072418 (1991-12-01), Boutaud et al.
patent: 5142625 (1992-08-01), Nakai
patent: RE34363 (1993-08-01), Freeman
patent: 5274570 (1993-12-01), Izumi et al.
patent: 5311114 (1994-05-01), Sambamurthy et al.
patent: 5339262 (1994-08-01), Rostoker et al.
patent: 5347181 (1994-09-01), Ashby et al.
patent: 5361373 (1994-11-01), Gilson
patent: 5457410 (1995-10-01), Ting
patent: 5473267 (1995-12-01), Stansfield
patent: 5500943 (1996-03-01), Ho et al.
patent: 5504738 (1996-04-01), Sambamurthy et al.
patent: 5537601 (1996-07-01), Kimura et al.
patent: 5543640 (1996-08-01), Sutherland et al.
patent: 5550782 (1996-08-01), Cliff et al.
patent: 5552722 (1996-09-01), Kean
patent: 5574930 (1996-11-01), Halverson, Jr. et al.
patent: 5574942 (1996-11-01), Colwell et al.
patent: 5581745 (1996-12-01), Muraoka et al.
patent: 5600845 (1997-02-01), Gilson
patent: 5652904 (1997-07-01), Trimberger
patent: 5671355 (1997-09-01), Collins
patent: 5705938 (1998-01-01), Kean
patent: 5732250 (1998-03-01), Bates et al.
patent: 5737631 (1998-04-01), Trimberger
patent: 5740404 (1998-04-01), Baji
patent: 5742179 (1998-04-01), Sasaki
patent: 5742180 (1998-04-01), DeHon et al.
patent: 5748979 (1998-05-01), Trimberger
patent: 5752035 (1998-05-01), Trimberger
patent: 5760607 (1998-06-01), Leeds et al.
patent: 5809517 (1998-09-01), Shimura
patent: 5835405 (1998-11-01), Tsui et al.
patent: 5874834 (1999-02-01), New
patent: 5889788 (1999-03-01), Pressly et al.
patent: 5892961 (1999-04-01), Trimberger
patent: 5914616 (1999-06-01), Young et al.
patent: 5914902 (1999-06-01), Lawrence et al.
patent: 5933023 (1999-08-01), Young
patent: 5970254 (1999-10-01), Cooke et al.
patent: 6011407 (2000-01-01), New
patent: 6020755 (2000-02-01), Andrews et al.
patent: 6026481 (2000-02-01), New et al.
patent: 6096091 (2000-08-01), Hartmann
patent: 6154051 (2000-11-01), Nguyen et al.
patent: 6163166 (2000-12-01), Bielby et al.
patent: 6172990 (2001-01-01), Deb et al.
patent: 6178541 (2001-01-01), Joly et al.
patent: 6181163 (2001-01-01), Agrawal et al.
patent: 6211697 (2001-04-01), Lien et al.
patent: 6242945 (2001-06-01), New
patent: 6272451 (2001-08-01), Mason et al.
patent: 6279045 (2001-08-01), Muthujumaraswathy et al.
patent: 6282627 (2001-08-01), Wong et al.
patent: 6301696 (2001-10-01), Lien et al.
patent: 6343207 (2002-01-01), Hessel et al.
patent: 6353331 (2002-03-01), Shimanek
patent: 6356987 (2002-03-01), Aulas
patent: 6389558 (2002-05-01), Herrmann et al.
patent: 6434735 (2002-08-01), Watkins
patent: 6460172 (2002-10-01), Insenser Farre et al.
patent: 6467009 (2002-10-01), Winegarden et al.
patent: 6483342 (2002-11-01), Britton et al.
patent: 6507942 (2003-01-01), Calderone et al.
patent: 6510548 (2003-01-01), Squires
patent: 6518787 (2003-02-01), Allegrucci et al.
patent: 6519753 (2003-02-01), Ang
patent: 6522167 (2003-02-01), Ansari et al.
patent: 6532572 (2003-03-01), Tetelbaum
patent: 6539508 (2003-03-01), Patrie et al.
patent: 6541991 (2003-04-01), Hornchek et al.
patent: 6578174 (2003-06-01), Zizzo
patent: 6587995 (2003-07-01), Duboc et al.
patent: 6588006 (2003-07-01), Watkins
patent: 6601227
Siek Vuthe
Tat Binh C.
Webostad W. Eric
Xilinx , Inc.
LandOfFree
Method and apparatus for routing interconnects to devices... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for routing interconnects to devices..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for routing interconnects to devices... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3313489