Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2005-04-05
2005-04-05
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06877148
ABSTRACT:
In one embodiment, the invention is a method. The method is a method of routing a circuit having a set of nets and a set of circuit elements specified as a slicing tree and a set of linear constraints. The method includes finding short paths for the set of nets based on a minimum-spanning-tree solution to a floorplan derived from the slicing tree for each net of the set of nets. The method also includes routing the nets as conductors within channels of the floorplan, the conductors having locations satisfying a set of linear constraints based on the solution of a linear optimization problem.
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Boyd Stephen
Fong Lungying
Hassibi Arash
Barcelona Design, Inc.
Blakely , Sokoloff, Taylor & Zafman LLP
Siek Vuthe
Tat Binh
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