Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
1998-11-03
2001-05-08
Sheikh, Ayaz R. (Department: 2781)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C711S170000, C711S105000, C710S010000, C710S301000, C713S001000
Reexamination Certificate
active
06230274
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present disclosure pertains to the field of data processing systems. More particularly, the present disclosure pertains to initializing or configuring memory devices in a memory channel and restoring memory devices when exiting a low power state.
2. Description of Related Art
Placing a computer system into a low power state is a well known technique for saving power. For example, the Advanced Configuration and Power Management Interface (ACPI) specification suggests the use of several low power states and defines the interfaces between the operating system software and system hardware.
A suspend-to-RAM (STR) state is a common state used in power management applications. Typically, when this low power state is entered, processing activity ceases, and certain values are stored in memory, preserving them for when processing resumes at a later point in time. For example, the ACPI S3 sleeping state is a state where all system context is lost except system memory. Processor and memory controller context (i.e., register and internal memory values) are lost in this state. Additionally, other power management techniques may include similar states in which the register and/or memory values in a chipset or memory controller are lost.
Losing memory controller values may be particularly problematic in a system that requires memory configuration registers to be initialized in order to communicate properly with the memory. Until such values are restored, the main memory can not be accessed. Moreover, the main memory cannot be used to store the configuration values or to store a program for restoring such values.
To restore values to such memory configuration registers, one approach would be to execute the entire memory initialization sequence to re-establish the lost initialization values. This approach, however, may be disadvantageous for two reasons. First, the initialization sequence may be lengthy, thereby causing a significant latency to occur when the system tries to wake up from a STR state. Secondly, the initialization sequence may perform some operations that jeopardize the contents of the memory. If memory were indeed lost by re-initializing the system, such an approach would not be practical for some implementations. For example, if exiting the ACPI S3 state corrupted memory, the implementation would not be compliant with the ACPI specification.
One bus that requires a significant amount of initialization prior to proper operation is a Rambus™ Direct Rambus Dynamic Random Access Memory channel (a Direct RDRAM™ channel). This bus is described in detail in documentation available from Rambus Corporation of Mountain View, Calif. Numerous memory controller values may be lost when a memory controller for a bus architecture like the Direct Rambus™ channel architecture is placed in a low power state, and the prior art may not provide an adequate mechanism to recover these values.
SUMMARY
A method and apparatus for restoring a memory device channel when exiting a low power state is disclosed. One method involves storing a set of memory initialization values from storage locations in a memory controller into a memory that maintains values during a power down state. The values may be necessary to access a system memory. When the power down state is exited, the values are restored to the storage locations in the memory controller.
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Rambus Advance Information—Direct RAC Data Sheet dated Aug. 7, 1998 .
Rambus Advance Information—Direct Rambus RIMM Module 128 MBytes (64Mx16/18) dated Aug. 20, 1998.
Rambus Advance Information—Direct RMC.d1 Data Sheet dated Aug. 8, 1998.
Rambus Advance Informaion—Direct RDRAM 64/72-Mbit (256Kx16/18x16d) Datasheet, Aug. 3, 1998.
Rambus Advance Information—RIMM Serial Presence Detect Application Note dated Sep. 9, 1997.
Rambus Advance Information—Direct RAC Data Sheet dated Aug. 7, 1998.
Rambus Advance Information—Direct RMC, d1 Data Sheet dated Aug. 7, 1998.
Rambus Advance Information—Direct RDRAM 64/72-Mbit (256K×16/18×16d) Datasheet
Rambus Advance Information—RIMM Serial Presence Detect Aplication Note dated Oct. 9, 1997.
Nizar Puthiya K.
Stevens William A.
Chung-Trans X.
Draeger Jeffrey S.
Intel Corporation
Sheikh Ayaz R.
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