Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-11-07
2006-11-07
Peugh, Brian R. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S140000, C711S169000
Reexamination Certificate
active
07133968
ABSTRACT:
An in-order single-issue microprocessor detects data cache misses generated by instructions behind a stalled instruction in the microprocessor pipeline and issues memory requests on the processor bus for the missing data so as to overlap with resolution of the stalled instruction, which may also be a cache miss. The data cache has pipeline stages that parallel portions of the main microprocessor pipeline. Replay buffers are employed to save the state, i.e., instructions and associated data addresses, of the parallel data cache stages so that instructions above the stalled instruction can continue to proceed down through the data cache and access the cache memory to generate cache misses. The data cache pipeline stages are restored upon detection that the stall will terminate. The bus requests for the missing data are issued only if the stalled instruction does not access a memory-mapped I/O region of the memory address space.
REFERENCES:
patent: 5404486 (1995-04-01), Frank et al.
patent: 5845101 (1998-12-01), Johnson et al.
patent: 6085292 (2000-07-01), McCormack et al.
patent: 6088788 (2000-07-01), Borkenhagen et al.
patent: 6145054 (2000-11-01), Mehrotra et al.
patent: 6154815 (2000-11-01), Hetherington et al.
patent: 6237073 (2001-05-01), Dean et al.
patent: 6308241 (2001-10-01), Simovich et al.
patent: 6421783 (2002-07-01), Liu et al.
patent: 6697932 (2004-02-01), Yoaz et al.
Gaskins Daruis D.
Henry G. Glenn
Hooker Rodney E.
Bradley Matthew
Davis E. Alan
Huffman James W.
IP-First, LLC.
Peugh Brian R.
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