Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
1998-04-09
2001-02-20
Yoo, Do Hyun (Department: 2759)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S154000, C711S166000, C710S013000, C713S100000
Reexamination Certificate
active
06192447
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to memories, and more particularly to resettable memories.
BACKGROUND OF THE INVENTION
In some digital devices, a set of registers is used to store values that determine how the device is configured, and how the device should operate. For example, a PCI bus interface uses resettable configuration space registers. From time to time it is necessary to reset the registers to a known “reset” value, for example, at cold start, or after a failure.
Typically, resettable registers operate as follows. Initially, the registers store the known reset value. During operation, other values can be written to the registers. After a reset, a read access to a particular register should produce the reset value, until the register has been written. After valid data has been written to a register, the registers can be read. In most cases, the reset is performed to all registers in a single time unit, for example, one cycle of the system clock.
Prior art approaches use resettable registers directly. A reset capability adds to the amount of circuitry required to implement a storage location. In some implementation technologies, particularly those relying on a restricted set of pre-diffused circuit structures, for example mask or field programmed gate arrays, (FPGA), the number of additional circuit elements needed to provide a reset capability can be substantial.
Therefore, there is a need for memories that can be reset to produce known values after a reset without substantially increasing the number of circuit elements.
SUMMARY OF THE INVENTION
The invention provides a resettable memory with a small number of additional circuit elements. A random access memory includes a plurality of memory locations, each memory location storing a plurality of bits. The number of locations and the number of bits stored in each location can be adjusted to the type and number of resettable registers that are required.
A separate single resettable register is associated with a plurality of bits, there is one bit for each of the plurality of memory locations. The resettable register can be cleared during a single clock cycle by a reset signal. Resetting the registers zeroes all bits, for example, making all corresponding memory locations invalid. A particular bit in the register is set to one by a write to the corresponding memory location. The memory location is now valid.
When reading a particular memory location while the corresponding bit in the register is invalid generates a reset value. The reset value can either be produced from a gated reset value register, or from one of the memory locations. In the first case, two gates are used to select data output either from the random access memory, or the reset value register depending on the state of the corresponding bit in the register. In the second case, the memory access address is recoded to a memory location that stores the reset value.
In one aspect of the invention, a read-only memory can be connected to the read/write signal inputs of the random access memory to provide fine-grained read-only and read/write access to the random access memory locations.
REFERENCES:
patent: 4638454 (1987-01-01), Waterworth
patent: 5230058 (1993-07-01), Kumar et al.
patent: 5257380 (1993-10-01), Lang
patent: 5432918 (1995-07-01), Stamm
patent: 5794033 (1998-08-01), Aldebert et al.
Compaq Computer Corporation
Moazzami Nasser
Oppenheimer Wolff & Donnelly LLP
Yoo Do Hyun
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