Method and apparatus for resetting a memory upon power recovery

Static information storage and retrieval – Magnetic bubbles – Guide structure

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365229, 364DIG1, 364273, 3642734, 36424691, 364DIG2, 3649649, 3649485, 3649489, G06F 1216

Patent

active

052049647

ABSTRACT:
A method and apparatus for resetting memory state when power is applied to the system. The memory has memory elements, a refresh clock and a refresh counter for counting refresh cycles and providing refresh signals to the memory elements, the memory elements and refresh means being connected from the power system and from a battery back-up means. A state detection means is connected from the refresh counter for detecting a change in state of the refresh counter to a state equivalent to the reset state of the refresh counter and asserting a state change signal. A means responsive to the state change signal and to the occurrence of the reset signal provides a memory controller reset signal, so that the memory controller reset signal occurs in synchronization with the change of state of the refresh counter to a state equivalent to the refresh counter reset state. The memory reset further includes a time-out counter means responsive to the assertion of the reset signal and to the refresh clock for counting refresh cycles in synchronization with the refresh counter. A time-out detection means is responsive to the time out counter means for providing a time out signal when the time-out counter has counted a refresh period plus one clock cycle and to the state change signal for providing the memory controller reset signal when the time-out counter has counted a refresh cycle plus one clock period and the state change signal has not been asserted.

REFERENCES:
patent: 4357686 (1982-11-01), Scheuneman
patent: 4977537 (1990-12-01), Dias

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