Method and apparatus for resetting a gray code counter

Electrical computers and digital processing systems: memory – Address formation – Incrementing – decrementing – or shifting circuitry

Reexamination Certificate

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Details

C711S166000, C365S221000, C345S556000, C345S558000, C710S053000

Reexamination Certificate

active

07636834

ABSTRACT:
Aspects of the invention may include gradually decrementing or incrementing a write pointer (370) associated with a data buffer such as the FIFO buffer (310) until a reset value of the write pointer (370) is reached in response to an indication that a data buffer controlled by the gray code counter is empty. Additionally, a read pointer (380) associated with the data buffer (310) may be gradually incremented or decremented until a reset value of the read pointer (380) is reached in response to an indication that the data buffer controlled by the gray code counter is full. The data buffer may be a first-in-first-out (FIFO) buffer such as FIFO buffer310, which may be asynchronously clocked. The data buffer may be adapted to buffer any one or a combination of video, voice and data.

REFERENCES:
patent: 4780894 (1988-10-01), Watkins et al.
patent: 5103499 (1992-04-01), Miner et al.
patent: 5365485 (1994-11-01), Ward et al.
patent: 5426756 (1995-06-01), Shyi et al.

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