Method and apparatus for reset-sensitive and controlled register

Details Method and apparatus for reset-sensitive and controlled register Method and apparatus for reset-sensitive and controlled register

1996-05-06

1998-07-07

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

711154, 364DIG1, G06F 1300

Patent

active

057784442

ABSTRACT:
A method for accessing a control register in a data processing system which ignores a first write to sensitive control bits when in a first mode, but allows subsequent writes to the sensitive control bits. When operating in a user mode, the method allows a first write to the sensitive control bits, but does not allow any subsequent writes. When a write access is made to the sensitive control bits during test mode only non-initial writes are effective. When a write access is made to the sensitive control bits during user mode only an initial write is effective. The method is effective in a data processing system having a control register write access scheme.

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