Reduction of bipolar gain and improvement in snap-back sustainin

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257344, 257347, 257350, 257408, H01L 2701, H01L 2976, H01L 2712, H01L 2994

Patent

active

053151445

ABSTRACT:
The gain of a parasitic lateral bipolar device in an MOS SOI structure is reduced to increase the differential between the snap-back sustaining voltage and the maximum recommended power supply voltage. Prior to insulated gate structure definition, very lightly doped source and drain regions are implanted to the underlying insulator layer. The source and drain regions have a doping concentration that is within an order of magnitude of the doping concentration of the well portion of the semiconductor layer. After the very lightly doped regions have been implanted, the implant mask is stripped and an insulated gate structure is formed atop the channel surface portion of the well layer between the source and drain regions. Using the insulated gate structure as a mask, off-axis, high angle implants of the same conductivity type as the source and drain regions are carried out to a first depth that only partially penetrates the depth of the deep source and drain implants. Very shallow high impurity concentration ohmic contact regions are then formed in surface portions of the first and second regions, and ohmic contact layers are formed on the conductive gate layer and the high impurity concentration ohmic contact regions.

REFERENCES:
patent: 4786955 (1988-11-01), Plus et al.

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