Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-10-03
2003-01-21
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C703S014000
Reexamination Certificate
active
06510543
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to methods of rendering images on a computer screen and in particular, to a method and apparatus for rendering an integrated circuit (“IC”) design layout.
BACKGROUND OF THE INVENTION
FIG. 1
illustrates a block diagram of a prior art system for rendering an integrated circuit design layout from cell-based information. The cell-based information in. this case is stored in GDS-II format in a GDS-II database
101
. A rendering engine
102
renders the integrated circuit design layout from the cell-based information by reading the cell-based information from the GDS-II database
101
, processing the cell-based information for a given zoom-in factor, and transmitting the processed information to a frame buffer
103
of a computer display screen. A computer operator viewing the integrated circuit design layout on the computer display screen selects the zoom-in factor.
One problem with such prior art system, however, is the time that it takes to render integrated circuit design layouts at low zoom-in factors on the computer screen. In particular, as integrated circuit devices pack more and more transistors on a chip, the rendering time gets increasingly slower to the point of being highly objectionable to the computer operator. This is because as more and more transistors are packed on a chip, the rendering engine must process more and more cells in the cell-based structure in order to render the integrated circuit design layout at low zoom-in factors.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method and apparatus for rendering an integrated circuit design layout that is relatively faster than prior art techniques.
Another object is to provide a method and apparatus for rendering an integrated circuit design layout that is relatively faster than prior art techniques at low zoom-in factors.
These and additional objects are accomplished by the various aspects of the present invention, wherein briefly stated, one aspect of the invention is a method of rendering an integrated circuit design layout, comprising: receiving a zoom-in factor; if the zoom-in factor is greater than a first number, then rendering an integrated circuit design layout by processing cell-based information of the integrated circuit design; and if the zoom-in factor is less than the first number, then rendering the integrated circuit design layout from at least a first graphics image of the integrated design layout.
Another aspect of the invention is an apparatus for rendering an integrated circuit design layout. The apparatus comprises a memory and at least one processor. The memory includes a first graphics file indicative of the integrated circuit design layout at a first selected zoom-in factor. The at least one processor includes a graphics processor, a rendering engine and a selector. The graphics processor serves to render the integrated circuit design layout from at least the first graphics file. The rendering engine serves to render the integrated circuit design layout from cell-based information. The selector serves to enable either the graphics processor or the rendering engine depending upon a received zoom-in factor. If the received zoom-in factor is less than the first selected zoom-in factor, then the selector enables the graphics processor. On the other hand, if the received zoom-in factor is greater than the first selected zoom-in factor, then the selector enables the rendering engine.
Additional objects, features and advantages of the various aspects of the present invention will become apparent from the following description of its preferred embodiments, which description should be taken in conjunction with the accompanying drawings.
REFERENCES:
patent: 5625568 (1997-04-01), Edwards et al.
patent: 6236956 (2001-05-01), Mantooth et al.
Chen Tsung-Yen (Eric)
Gu Ke-Qin
Han Ching-Chih (Jason)
Lee Kuo-Chun
Okumoto Victor H.
Oridus Inc.
Rossoshek H
Siek Vuthe
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