Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2000-07-27
2003-11-25
Kim, Matthew (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C711S158000, C711S151000, C711S168000, C711S137000, C711S138000, C711S157000
Reexamination Certificate
active
06654860
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to computer systems and more particularly to memory control functions within computer systems.
2. Description of the Related Art
In conventional computer systems, such as personal computer systems utilizing x86 based processors, the processor, along with other components in the computer system, are coupled to main system memory through an integrated circuit known in the art as the “North Bridge.” The North Bridge provides a memory control function as well as a bridge function between the host bus connecting the processor and system input/output buses such as the Peripheral Component Interconnect (PCI) bus and the devices connected to the PCI bus.
In current architectures, the PCI bus provides the major I/O bus for the computer system. Other buses are commonly found in conventional computer systems. One such bus is the Universal Serial Bus (USB) bus and another bus is the IEEE 1394 bus. USB and 1394 traffic typically communicate with memory through a South Bridge integrated circuit, which is coupled to the PCI bus. The South Bridge provides a bridge function between the PCI bus and other buses. In addition, the South Bridge provides for communication with a variety of legacy devices, provides power management functions, etc. In any case, the buses at issue, and the devices which couple to those buses access system memory through the PCI bus.
One exception is a graphics bus, the Accelerated Graphics Port (AGP), which has been developed to both (1) reduce the load on the PCI bus systems, and (2) extend the graphics capabilities of systems. The AGP interface standard (defined by Accelerated Graphics Port Interface Specification, Revision 1.0 (Jul. 31, 1996) from Intel Corporation) allows the graphics processor to retrieve graphics information from system memory independently of the PCI.
In current industry architectures, the host bus, the AGP interconnect, and the PCI bus access system memory through the memory controller in the North Bridge. The memory controller maps logical addresses used by the processor to physical locations in system memory. The system memory controlled by the North Bridge is typically made up of a plurality of Direct Random Access Memory chips (DRAMs).
There are a number of different types of DRAMs including RDRAM (Rambus DRAMS), SDRAM (Synchronous DRAMs), DDRSDRAM (Double data rate SDRAMs). DRAM technology continues to evolve. DRAMs are organized into various banks. Each bank is comprised of a matrix of storage locations organized in rows and columns. Each of the rows typically shares sense amplifiers. When a memory access occurs, such as a read cycle, the memory controller receives an address over one of the buses, maps the received address into an appropriate physical address and performs the access operation to system memory. Consequently, an address, which for sake of illustration will be assumed to be 16 bits long, customarily is conceived of as being composed of two parts: a first 8-bit portion of the address which is associated with a row address, and a second 8-bit portion which is associated with a column address (again, the bit lengths are hypothetical and merely utilized here for illustrative purposes). This separation of the address into row and column portions allows the address to correctly specify a storage location, or cell, by its row and column.
In order to minimize the number of pins on the DRAM, memory accesses in conventional DRAMs typically place the row portion of the address on the address bus to select the appropriate row, and then place the column portion of the address on the address bus to select the appropriate column. At some time after the row and column information have both been specified, the data from the memory location specified by the row and column address appears on the DRAM data bus.
From the foregoing, it can be seen that in order to make a single memory access there are three phases: a row address phase, a column address phase, and a data retrieval phase. In the past, it was noticed that typical programs tend to operate sequentially, so if there is a memory address accessed, it is likely that the next memory address accessed will be the very next cell, which means that the column address is likely to change, while the row address is not likely to change. Consequently, typical DRAMs are structured such that once the row address has been provided, thereafter DRAMS can continue to access the row (also referred to herein as page) that is “open” in the DRAM.
As an access approaches a last column address in a row, it is typical that the next sequential physical address is located in another bank. That is because accessing another page or row in the same bank requires that the currently open page be closed. Thus, the row in the new bank, if not already open, has to be precharged and then the new row in that bank can be opened and accessed. The new row may be opened using an appropriate command for the memory device after it is precharged and accessed.
In the event that a memory controller has several memory accesses to be done sequentially, then once a page is open it would make sense (but it is not currently done in the art) from an efficiency standpoint to examine pending as well as current memory accesses in order to determine which of those pending memory accesses will be to memory locations that are within a currently open page (that is, the row of the request is the row from which a memory controller is currently reading within a DRAM). In other words, assuming a page X is open, if there are four memory accesses A, B, C, and D, waiting to be performed, and assuming the first access A is to page Z, the second access B is to page X, the third access C is to page Y, and the fourth access D is to page W, it is preferable from a memory efficiency standpoint that the data access (i.e., access B) appropriate to the page that is open (i.e., page X) be made first.
Current memory controllers do not typically “look ahead” to see if certain pending memory accesses are destined for currently open pages based on the type of stream that is currently accessing memory. Furthermore, at any given time, typically more than one page of memory is generally open and in future systems this will become more likely. For example, under the Direct RDRAM scheme, it is expected that up to 8 pages per RDRAM chip will be open simultaneously. Thus, if a system has eight RDRAM chips (a reasonable assumption), it will be possible to have up to 64 pages open simultaneously.
Controlling memory access via the use of “look ahead” would be undeniably valuable. Furthermore, as the foregoing has shown, the prospective ability of the memory controllers to schedule memory access on the basis of look ahead is likely to become even more important in that future system memories are likely to be able to provide a very large number of open pages of memory simultaneously. It is therefore apparent that a need exists in the art for a method and system which will provide data processing systems, having memory controllers, with the ability to look ahead and intelligently schedule accesses to system memory utilizing information gained from such looking ahead.
In addition to the foregoing, it has been noted that multiple devices (e.g., one or more CPUs, PCI bus devices, 1394 devices, and network devices) communicate over various different buses in order to access data processing system memory through a memory controller. Further, there is an increase in applications having isochronous data, such as from multimedia streams. Isochronous data has throughput requirements that must be met or the user of the application will be negatively impacted. For example, if the next frame in a video steam is late, the picture can be degraded. In contrast to isochronous streams, asynchronous streams do not have specific throughput requirements but the goal is generally to keep latency for asynchronous streams to a minimum to maximize system performance.
Different types of devices have differen
Qureshi Qadeer Ahmad
Strongin Geoffrey S. S.
Elmore Stephen
Kim Matthew
Zagorin O'Brien & Graham LLP
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