Etching a substrate: processes – Nongaseous phase etching of substrate – Projecting etchant against a moving substrate or controlling...
Reexamination Certificate
2001-12-21
2003-11-18
Alanko, Anita (Department: 1765)
Etching a substrate: processes
Nongaseous phase etching of substrate
Projecting etchant against a moving substrate or controlling...
C216S100000, C216S105000, C216S106000, C156S345190, C156S345230, C156S345510, C156S915000, C438S401000, C438S748000, C438S754000, C438S975000
Reexamination Certificate
active
06649077
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to a method and apparatus for removing coating layers from alignment marks on a wafer positioned in a spin processor and more particularly, relates to a method and apparatus for removing coating layers from alignment marks on a wafer by placing the wafer face down on an edge ring equipped with tab sections spaced-apart from the alignment marks such that an etchant for the coating layers can be drawn into the gap formed between the tab sections and the alignment marks to remove the coating layers by capillary action.
BACKGROUND OF THE INVENTION
Deposition and patterning are two of the basic steps performed in semiconductor processing. Patterning is also referred to as photolithography, masking, oxide or metal removal, and microlithography. Patterning enables the selective removal of material deposited on a semiconductor substrate, or wafer, as a result of deposition. For example, as shown in
FIG. 1A
, a layer
104
has been deposited on a substrate
102
. After the photolithography process is performed, as shown in
FIG. 1B
, some parts of the layer
104
have been selectively removed, such that gaps
106
a
and
106
b
are present within the layer
104
. A photomask, or pattern, is used (not shown in
FIG. 1B
) so that only the material from the gaps
106
a
and
106
b
are removed, and not the other portions of the layer
104
. The process of adding layers and removing selective parts of them, in conjunction with other processes, permits the fabrication of semiconductor devices.
Alignment is critical in photolithography and deposition, as well as in other semiconductor processes. If layers are not deposited properly, or if they are not selectively removed properly, the resulting semiconductor devices may not function, relegating them to scrap, which can be costly. Therefore, alignment marks are placed on the semiconductor wafer for the proper positioning during the deposition and photolithography processes. This is shown in
FIG. 2
, where the semiconductor wafer
202
has alignment marks, such as the alignment square
204
, thereon. When the photomask
206
is positioned over the wafer
202
, its own alignment marks, such as the alignment square
208
, is aligned with the alignment marks of the wafer
202
. For example, the alignment square
208
of the photomask
206
is aligned so that the alignment square
204
of the wafer
202
is centered therein.
Alignment is especially critical where more a number of metal or other layers have already been deposited on the wafer. Subsequent deposition of silicon dioxide or other layers in such instances usually requires that the alignment marks on the wafer be exposed for proper overlay of the silicon dioxide or other layers. While a mask may prevent the layers themselves from obfuscating the alignment marks, the photoresist used to pattern or perform other processing of these layers cannot be masked, and covers or at least blurs the alignment marks. Without clear exposure of the alignment marks, however, overlay misalignment can result. Overlay misalignment is also referred to as overlay registration error. Misalignment is a serious problem, and can result in significant semiconductor wafer scrap. Wafer scrap can sometimes be reused, but often is discarded, resulting in added costs incurred by the semiconductor foundry.
In the recent development of semiconductor fabrication technologies, copper has been widely used in devices of 0.18 &mgr;m or smaller as vias or interconnects. A widely used technique for depositing copper on a semiconductor wafer is the electro-chemical plating method. However, when copper is deposited onto a wafer surface by the electro-chemical plating method, alignment marks on the wafer are also covered with copper and a layer of TaN which is a diffusion barrier for copper. If the Cu/TaN layers formed over the alignment marks are not removed completely in a later process, alignment failure can occur in a future photolithographic step.
Presently, a process of edge/bevel cleaning is used to remove a circular band of Cu/TaN at the wafer edge. This is shown in FIG.
3
. Wafer
302
, which has alignment marks
304
and
306
formed on an active surface
308
, is cleaned by using a cleaning solution such that a circular band
310
of Cu/TaN at the wafer edge can be removed. Although the Cu/TaN layers over the alignment marks
304
,
306
are removed, the cleaning process inevitably results in severe die loss along the circular band
310
. For instance, as shown in
FIG. 3
, IC dies
312
~
330
are all lost due to the Cu/TaN cleaning process.
It is therefore an object of the present invention to provide a method for removing coating layers from alignment marks on a wafer that does not have the drawbacks or shortcomings of the conventional methods.
It is another object of the present invention to provide a method for removing coating layers from alignment marks on a wafer positioned in a spin processor by mounting the wafer juxtaposed to an edge ring.
It is a further object of the present invention to provide a method for removing coating layers from alignment marks on a wafer by providing an edge ring that is equipped with at least one tab section for overlapping a corresponding alignment mark on the wafer.
It is another further object of the present invention to provide a method for removing coating layers from alignment marks on a wafer by suspending the wafer over a wafer pedestal by an inert gas flow and flowing an etchant onto the backside of the wafer while the wafer is rotated.
It is still another object of the present invention to provide a method for removing coating layers from alignment marks situated on a wafer by suspending the wafer over an edge ring such that a distance of less than 5 mm is kept between the wafer and the edge ring.
It is yet another object of the present invention to provide an apparatus for removing coating layers from alignment marks on a wafer which includes a spin processor, a rotatable wafer pedestal, an edge ring for mounting on the pedestal, a mechanical clamp for holding the wafer during rotation, a rotating means for rotating the wafer pedestal, and a nozzle for flowing an etchant onto a backside of the wafer.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method and an apparatus for removing coating layers from alignment marks on a wafer are provided.
In a preferred embodiment, a method for removing coating layers from the top of alignment marks on a wafer positioned in a spin processor is provided which includes the steps of providing a spin processor equipped with a rotatable wafer chuck therein, the wafer chuck is provided with inert gas flow channels for flowing an inert gas in an upward direction; providing a wafer that has at least one alignment mark on an active surface, the at least one alignment mark is covered with a coating layer; mounting an edge ring on an outer periphery of the wafer chuck, the edge ring has at least one tab section extending outwardly from an inner periphery of the edge ring toward a center of the ring, each of the at least one tab section has an area sufficiently large to overlap one of the at least one alignment mark; positioning the wafer with the active surface in a faced down position on the edge ring supported by the inert gas flow from the inert gas flow channels such that each one of the at least one alignment mark on the wafer overlaps and suspends over each one of the at least one tab section on the edge ring by a preset distance of not more than 5 mm; and rotating the wafer chuck and the edge ring with the wafer suspended thereon and flowing an etchant onto a backside of the wafer such that the etchant is drawn into the gap to remove the coating layers by capillary action.
In the method for removing coating layers from the top of alignment marks on a wafer positioned in a spin processor, the coating layer on the alignment mark is an electroplated Cu layer. The method may further include the step of flowing N
2
gas upwardly through the wafer chuck to
Hu Tien-Chen
Ku Wei-Cheng
Tsai Pang-Yen
Yang Sen-Shan
Alanko Anita
Taiwan Semiconductor Manufacturing Co. Ltd
tung & Associates
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