Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-12-21
2002-02-26
Follansbee, John A. (Department: 2154)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
Reexamination Certificate
active
06351822
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to remapping computer data. More particularly the present invention relates to remapping read-only memory.
BACKGROUND OF THE INVENTION
In Read Only Memory (ROM) configurations, it is frequently desired to modify the ROM; i. e., a damaged area of the ROM may be repaired thereby, or changes to the data stored on said ROM such as upgrades or changes to eliminate “bugs” may need to be made without replacing the ROM.
In order to modify the ROM, the area to be modified must be defined in some way. Historically, the address at which a patch is to be substituted is stored in a table, and the table is consulted whenever a ROM access is made to determine if a patch exists for that address of the ROM.
Testing each address of the ROM as discussed above works well with relatively few patches, such as in a system with a lightly loaded central processor, where accessing the table has little impact on performance. However, using a lookup table to determine whether a patch is needed can be a significant problem when many patches on a large system are associated with a busy processor; or high-speed, where latency becomes an issue, and performance can be significantly impacted thereby.
Another problem is that when a small part of a ROM is damaged or includes errors or “bugs”, the section to be patched may constitute one or more pieces of a routine; that is, a defined task with specific steps to be accomplished. Because patches may be randomly distributed, performance may become indeterminate due to the need to incorporate the patches. Critical scheduling such as for “real time” applications, may be jeopardized by patches. Prior art also utilized remapping mechanisms which utilized a table based upon an earlier instruction match to gain time for remapping. Those schemes require sequential execution of instructions. The current invention overcomes this restriction and other disadvantages of the prior art.
SUMMARY OF THE INVENTION
First some definitions that are useful in understanding the following description of the invention are provided.
As used herein and generally, when software is originated or revised, the software may be treated as “data segments” in which meaningful pieces of code (software) may be defined, just as in normal writing, paragraphs are defined (or chapters, etc.). This results in advantageous places for placing markers, something like “bookmarks”. With normal paragraphs, a tab is often used; with software code, a subroutine name is created. Just as in writing text, the tab (or subroutine name) has no special meaning, but is inserted because it may be helpful. In the present invention, the subroutine name is used in just that way, to identify an enabler segment beginning, just as a tab may be used to identify a paragraph beginning and further for remapping purposes. Like a tab at the beginning of a paragraph, a token may be placed at each or any subroutine beginning, not to identify a beginning, but merely an alert that signals a data segment may be remapped there without penalty. This token may be a No Operation (NOP) instruction, or may be any instruction whose execution is non-destructive, or non-functional, e.g. a READ instruction. A READ instruction, in most applications, fetches data to the processor, but by itself, causes no action.
When a data segment is initially created, or when existing data segments are revised, such as a data segment for which patching in accordance with the present invention may be desired, entry points may be advantageously included. As an example, the initial boundary of a subroutine might be defined; where the subroutine is both an integral part of one routine, and simultaneously a callable subroutine for a second routine; or have some other significance as an advantageous place for initiating a routine; a token, such as a software No Operation (NOP), is placed in the data. Note that it is generally accepted in the art that instructions as well as information are lumped together generically as “data”; so a NOP, which is technically an instruction similar to a one cycle “pause” command, is referred to herein as “data”. A NOP is advantageous for remapping because, in addition to acting as a token, a NOP idles the machine for one cycle.
In the present invention, the machine has instruction fetches located by instruction address, such as in its operating system (OS), that instruct the machine to refer to a lookup table on encountering each instruction address. As directed by a lookup table or other means, the instruction fetch can then be redirected to an alternate source rather than the original source ROM. This can be especially advantageous if the alternate source is re-writeable, since a ROM chip can be saved by branching around a defective section or to an alternate program path.
The present invented method enables remapping to work successfully with microcontrollers and microprocessors which fetch instructions within a single clock cycle.
The method of the present invention enables remapping to work with microcontrollers which operate at high speed to fetch and preferably fetch and execute instructions within a single clock cycle. The present method includes using a target pointer which does not remap the current access, but forces a slower fetch on the next subsequent access upon lookup detection of a branch to a remapped data section. It should be noted that the instruction (i.e. the token) is executed, which differentiates this design. This enables remap on extremely fast devices which go through a single cycle too quickly to enable both the detection of the existence of the remap branch and continue the program execution in a single cycle, while also advising the processor of a “Remapped” subsequent access in time for execution.
The present method includes using a non-destructive instruction, e.g. NOP, as the first instruction of a routine or callable subroutine to provide additional latency for a remapping match hardware to provide alternate remapped data. The method further entails allowing the next instruction after the NOP (i.e. the first “remapped” instruction) to be executed in an equally fast or a slow mode as determined by the remapping hardware pointing to the first location to be remapped. This allows for placing the remapping pointer in only one place, i.e. at or immediately preceding a NOP instruction or other non-destructive instruction. This also allows multi-way entry into the routine, i.e. this allows entering the fetch routine for the remapped data from multiple places, without the requirement of knowing the previous fetch address. At the end of the patch which is brought in by this sequence, an instruction such as a jump or branch returns the data flow to the original code stream so that only an entry point as discussed above need be placed in the data to exercise the present method. It should be noted, that some code patches may not return to their point of origin, and depending on the code patch, make execute an entirely new program.
In setting up the ROM, the token instructions are placed at the beginning of routines or subroutines comprising data which are identified as being so far unproven, and posing a risk of including a bug. According to the present invention, after testing of the disc drive which includes this ROM, upon detection that in fact a bug does occur in some routine following a NOP instruction, then the necessary address to be detected by a comparator during or immediately preceding the NOP instruction will provide the data needed to branch to the remapped data as stored in a fast or slow alternate source.
The present invention provides the ability to map out a section of memory on a device which is extremely fast to an alternate source memory which may be equally fast, or otherwise to another memory which may be substantially slower.
In fact, the present invention, would allow the use of mapping from memory to a multiple of locations, some fast, some remapped data being stored in a fast alternate source memory, some remapped data being s
Masiewicz John Chester
Wright John Marc
Buenzow Jennifer
Cesari Kirk
Dempster Shawn
Follansbee John A.
Seagate Technology LLC
LandOfFree
Method and apparatus for remapping read only memory locations does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and apparatus for remapping read only memory locations, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and apparatus for remapping read only memory locations will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2940473