Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2007-04-17
2007-04-17
Verbrugge, Kevin (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S130000, C711S143000, C711S144000, C711S150000, C711S151000, C711S156000, C711S158000, C718S107000
Reexamination Certificate
active
10895519
ABSTRACT:
One embodiment of the present invention provides a system for releasing a memory location from transactional program execution. The system operates by executing a sequence of instructions during transactional program execution, wherein memory locations involved in the transactional program execution are monitored to detect interfering accesses from other threads, and wherein changes made during transactional execution are not committed until transactional execution completes without encountering an interfering data access from another thread. Upon encountering a release instruction for a memory location during the transactional program execution, the system modifies state information within the processor to release the memory location from monitoring. The system also executes a commit-and-start-new-transaction instruction, wherein the commit-and-start-new-transaction instruction atomically commits the transaction's stores, thereby removing them from the transaction's write set while the transaction's read set remains unaffected.
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Chaudhry Shailender
Herlihy Maurice P.
Jacobson Quinn A.
Moir Mark S.
Tremblay Marc
Park Vaughan & Fleming LLP
Sun Microsystems Inc.
Verbrugge Kevin
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