Method and apparatus for refreshing a non-clocked memory

Details Method and apparatus for refreshing a non-clocked memory Method and apparatus for refreshing a non-clocked memory

1997-12-22

2000-05-02

Nguyen, Hiep T

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711 5, 711173, 365222, 36523003, 36523005, 713600, G06F 1206

Patent

active

060584513

ABSTRACT:
An optimized memory refresh scheme controls and reduces instantaneous power consumption and power-related noise during DRAM refresh. In the optimized refresh implementation the DRAM is refreshed using a selectable overlap Column Address Select (CAS) before Row Address Select (RAS) refresh mode. A refresh interface between a host port and the memory system is over two bussed signals comprised of a Refresh Enable signal (Refresh.sub.-- Enable) and a Refresh Strobe pulse train (Refresh.sub.-- Strobe). Refresh.sub.-- Enable is issued by the host port to define a refresh operation. Refresh.sub.-- Strobe is a pulse train generated by the host port which is used as a clock for a sequential refresh sequencer. A refresh sequencer issues selectably timed column address refresh and row address refresh signals according to which the memory banks can all be selectably refreshed substantially in parallel, or with a predetermined selected level of overlap. Optimized skewing can be implemented to minimize the time for refresh. Refreshing of different memory banks can be selectably overlapped to provide acceptable current and noise profiles during refresh.

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patent: 5893927 (1999-04-01), Hovis
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