Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates – Field-effect transistor
Reexamination Certificate
2000-12-05
2003-08-05
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
Field-effect transistor
C326S095000
Reexamination Certificate
active
06603333
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to the field of dynamic logic circuits. More particularly, this invention relates to techniques for protecting dynamic logic circuits from noise at the inputs.
BACKGROUND OF THE INVENTION
Dynamic logic circuits are designed to operate at high speeds. They operate in two phases or cycles, a pre-charge phase or cycle and an evaluate phase or cycle. During the precharge phase or cycle, the voltage level at an output node of the dynamic logic circuit is precharged toward a high voltage level. During the evaluate phase or cycle, the voltage level at the output node is evaluated, in which case it may remain at the high level or it may be driven down toward a low voltage or ground level, depending upon the inputs to the circuit and the circuit functional design. However, dynamic logic circuits are often highly sensitive to noise at their inputs. In some dynamic logic circuits, noise at the inputs can lead to a “false evaluate”. This means the voltage at the output node may fail to fully charge due to noise at the inputs during the precharge phase before the circuit is ready to be evaluated. This could lead to false evaluate results during the evaluate phase or cycle which can affect the overall performance of the dynamic logic circuit. There are several prior art techniques for reducing noise sensitivity.
FIG. 1
illustrates a first prior art technique for reducing noise sensitivity in dynamic logic circuits. As shown in
FIG. 1
, a dynamic logic NAND gate is comprised of a number of transistors. A first P type transistor
102
is used to couple an output node O to a high voltage rail Vdd, in order to precharge a voltage level at the output node toward the high voltage rail Vdd when the clock signal CLK is low. This is known as the precharge phase or cycle.
Three N type transistors
103
,
104
and
107
operate as a current flow or evaluate path for coupling the output node O to a low voltage or ground rail GND. During the evaluate phase or cycle, the clock signal CLK is high, which causes the first P type transistor
102
to turn off and the third N type transistor
107
to activate. Dependent upon the inputs A and B, the transistors
103
and
104
may activate during the evaluate phase or cycle, allowing current to flow from the output node O toward the low voltage or ground rail GND, thereby driving the voltage level at the output node back toward the low voltage or ground level GND.
In the prior technique for protecting the dynamic logic circuit from noise which is illustrated in
FIG. 1
, each input A and B into the dynamic logic circuit
101
, is passed through a pair of inverters. Accordingly, the input A is passed through inverters
105
a
and
106
a
before it is coupled to the dynamic logic circuit
101
. Likewise, the input B is passed through inverters
105
b
and
106
b
before it is coupled to the dynamic logic circuit
101
. The use of an inverter pair for each input prevents moderate noise on either input A or B from activating the current flow or evaluate path between the output node O and the low voltage or ground rail GND before the inputs are valid. This ensures that the voltage level at the output node O is fully precharged to the high voltage level during the precharge phase or cycle.
The inverters will only allow the inputs A and B to the dynamic logic circuit
101
to trigger a discharge of current from the output node through the current flow or evaluate path if the inputs A and B are both at voltage levels above the activation levels of the inverters
105
a-b
and
106
a-b
. Therefore, the circuit
101
is not as susceptible or sensitive to noise at the inputs A and B because the two inverters in each inverter pair will not both activate when noise is present. However, use of the inverter pair at each input A and B slows down the proper operation of the dynamic logic circuit during the evaluate phase or cycle. The delay imposed through the use of a dual inverter configuration may be significant and is undesirable in most dynamic logic circuit design applications.
FIG. 2
illustrates a technique for reducing noise sensitivity in dynamic logic circuits using a NAND logic gate comprised of a number of transistors. A first P type transistor
202
is used to couple an output node O to a high voltage rail Vdd, in order to precharge a voltage level of output node O towards a high voltage rail Vdd when the clock signal CLK is low. This is known as the precharge phase or cycle.
Further, three different N type transistors
203
,
204
and
207
are coupled together serially and operate as a current flow or evaluate path in order to couple the output node O of the dynamic logic circuit to a low voltage or ground rail GND. Two of the N type transistors
203
and
204
have their respective gates coupled to receive one of the two inputs A and B. The third N type transistor
207
has its gate coupled to receive the clock signal CLK.
As explained earlier, when the clock signal CLK is active, the circuit is in the evaluate phase or cycle. When this occurs, the first P type transistor
202
is turned off and the third N type transistor
207
is active. The inputs A and B may then activate the two other N type transistors
203
and
204
; in which case, the voltage at the output node O will be driven toward the low voltage or ground rail GND.
In
FIG. 2
, the dynamic logic circuit is protected from noise at either of the inputs through the use of a pair of P type transistors
210
and
211
. Each P type transistor has its source coupled to the high voltage rail Vdd and its drain coupled to the drain of one of the N type transistors (the P type transistor
210
has its drain coupled to the drain of the N type transistor
203
, while the P type transistor
211
has its drain coupled to the drain of the N type transistor
204
). Each P type transistor
210
and
211
has its gate coupled to receive one of the inputs A or B. The two P type transistors
210
and
211
are preferably configured to activate only when a voltage equal to or greater than one half of the voltage level at the high voltage rail Vdd is applied to the gate of either transistor. Accordingly, in one preferred embodiment, unless the inputs A and B are both at voltage levels greater than ½ Vdd. the voltage at the output node O remains fully charged. This protects the circuit from erroneously discharging if noise appears at either input A or B. It is understood, that the two P type transistors
210
and
211
may be adjusted to require higher turn-on or activation voltages in order to increase the level of noise protection provided.
The method for protecting against noise in dynamic circuits illustrated in
FIG. 2
is more desirable than using the dual inverter design illustrated in
FIG. 1
since it does not significantly delay operation of the circuit. However, this method will not work in all dynamic logic circuits. For example, this method will not work in dynamic logic OR gates or NOR gates.
FIG. 3
illustrates a dynamic logic NOR gate which has no noise protection circuitry.
As shown in
FIG. 3
, the dynamic NOR gate
301
is comprised of a single P type transistor
305
which is coupled to three different N type transistors
306
,
307
and
308
which are arranged in parallel. The P type transistor
305
has its source coupled to a high voltage source Vdd, its drain coupled to an output node O, and its gate coupled to receive a clock signal CLK as an input. The P type transistor
305
is activated whenever the clock signal CLK is low, and a voltage level at the output node O is driven toward the high voltage rail Vdd. This occurs when the NOR gate
301
is in the precharge phase or cycle.
The three different N type transistors
306
,
307
and
308
are all coupled in parallel, such that each N type transistor has its drain coupled to the output node O, and its source coupled to a common node CN. The first N type transistor
306
has its gate coupled to receive an input signal A. The second N type transistor
307
has its gate coupled to receive an
Grondalski Robert S.
Naini Ajay
Srivastava Pranjal
Vinh James
Fenwick & West LLP
Fujitsu Limited
Tokar Michael
Tran Anh
LandOfFree
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