Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1995-04-27
1997-10-21
Bocure, Tesfaldet
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
370102, 3701053, H04L 700, H04J 307
Patent
active
056804229
ABSTRACT:
A wander reduction mechanism in an HDSL pulse-stuffing synchronization system provides a more precise measure of the phase of the incoming asynchronous signal than is obtained in conventional schemes, in which the only information available is the presence or absence of stuffing pulses. An auxiliary phase comparator and phase adjuster are incorporated into the synchronizer-multiplexer to generate a reference data clock (derived from the synchronized data clock), so that the incoming unsynchronized data clock can be tracked. As the clock is iteratively phase-adjusted, the respective changes are accumulated. At the end of a prescribed measurement interval, the net contents of the accumulator are encoded and transported over the synchronous digital data communication channel to the receiver. By decoding this sequence information, the desynchronizer is able to generate a desynchronized data clock having the same number of net phase adjustments during a measurement period as the reference clock at the synchronizer.
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Burch Richard A.
Rochell Timothy D.
Schneider Kevin W.
Turner Michael D.
Adtran
Bocure Tesfaldet
Wands Charles E.
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