Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
1999-10-19
2002-07-09
Fahmy, Wael (Department: 2823)
Semiconductor device manufacturing: process
With measuring or testing
C438S680000, C438S778000, C427S255110, C427S255210, C118S718000, C118S719000, C414S217000, C414S222020, C414S935000
Reexamination Certificate
active
06417014
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor device manufacturing, and more particularly, to a method and apparatus for reducing wafer to wafer deposition variation.
2. Description of the Related Art
In the manufacture of semiconductor devices, wafers, such as silicon wafers, are subjected to a number of processing steps. The processing steps include depositing or forming layers, patterning the layers, and removing portions of the layers to define features on the wafer. One such process step is the formation of a layer by chemical vapor deposition (CVD), where reactive gases are introduced into a vessel, e.g. a CVD tool, containing the semiconductor wafers. The reactive gases facilitate a chemical reaction that causes a layer to form on the wafers.
As the CVD tool is used repeatedly, material builds up on the internal surfaces of the tool, eventually affecting the deposition rate. Preventative maintenance procedures are performed periodically to remove this buildup and stabilize the deposition rate. The CVD tool is subject to numerous idle times, including the times preventative maintenance is performed, where the temperature of the tool is maintained at a level significantly less than its operating temperature. Other reasons for idle time include periodic testing or calibration and delays caused by other tools (not shown) upstream in the processing line.
In one illustrative CVD tool, the tool includes a heating block for maintaining the temperature of the tool during processing in accordance with a predetermined recipe, and a gas inlet for introducing reactive gases into the vessel. When the tool is brought back into service after an idle period, there is inherent variability in the deposition rate of the tool due to changes in the thermal characteristics of the tool. This variability exists until the tool has been operating for a period of time under steady state conditions. Generally, the heating lock is a large plate of aluminum, having a considerable thermal mass. The temperature of the gas inlet, often referred to as the shower head, and the emissivity of the wafer also affect the deposition rate during the initial start up.
A known technique for addressing this variability includes changing the temperature parameters (e.g., starting temperature and temperature ramp rate) in the recipe of the tool during the ramp up period. Changing the temperature affects the deposition rate, thus trying to compensate for the deposition rate variation during the ramp up period. Measurements of the deposition thickness are taken for each wafer and the temperature parameters are manually changed in response to the thickness feedback for subsequent wafers. If the thickness of the deposited wafer is not within tolerances, the wafer is re-worked (e.g., polished if too thick or subjected to another deposition if too thin). This rework is costly because it ties up the tools necessary for the rework to process only a limited number of wafers.
Adjusting the temperature, as described above, has precision limitations. First, the large thermal mass of the tool causes stability problems for the changing temperatures. Second, typical thermocouples used for controlling the temperature of the tool have an accuracy of ×3 or 4 degrees Celsius. The temperature adjustments made during the ramp up period are about 10° C. Thus, the inherent inaccuracy of the thermocouple for this fine of a temperature change also adds instability to the system. These instabilities increase the likelihood that the thickness of the deposited layer will not be within acceptable limits and the wafer will require rework.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.
SUMMARY OF THE INVENTION
One aspect of the present invention is seen in a processing line including a processing tool and an automatic process controller. The processing tool is adapted to deposit a layer of material on a semiconductor wafer based on an operating recipe. The automatic process controller is adapted to identify a post-idle set of wafers to be processed in the processing tool after an idle period, determine deposition times for wafers in the set of post-idle wafers, and modify the operating recipe of the processing tool for each of the wafers in the post-idle set based on the deposition times.
Another aspect of the present invention is seen in a method for reducing wafer to wafer deposition variation. The method includes designating a set of post-idle wafers; determining a deposition time for each of the wafers in the post-idle set, at least two of the deposition times being different; and depositing a layer on the wafers in the post-idle set based on the deposition times determined.
REFERENCES:
patent: 5494494 (1996-02-01), Mizuno et al.
patent: 5512320 (1996-04-01), Turner et al.
patent: 5943230 (1999-08-01), Rinnen et al.
Lam Kin-Sang
Sun Sey-Ping
Fahmy Wael
Lee Hsien-Ming
Williams, Mason & Amerson, P.C.
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