Method and apparatus for reducing timing pessimism during...

Details Method and apparatus for reducing timing pessimism during... Method and apparatus for reducing timing pessimism during...

2007-06-26

2007-06-26

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

10972899

ABSTRACT:
One embodiment of the present invention provides a system that reduces timing pessimism during Static Timing Analysis (STA). During operation, the system receives parametric variation data which describes the on-chip variation of timing-related parameters. Next, the system computes region-specific derating factors using the parametric variation data. The system then identifies a set of worst-case violating paths using the region-specific derating factors. Next, the system computes path-specific derating factors for one or more paths in the set of worst-case violating paths using the parametric variation data and the path properties. Finally, the system identifies zero or more realistic-case violating paths from the set of worst-case violating paths using the path-specific derating factors.

REFERENCES:
patent: 5845233 (1998-12-01), Fishburn
patent: 2003/0182098 (2003-09-01), Ehrler
patent: 2004/0167756 (2004-08-01), Yonezawa
patent: 2004/0243964 (2004-12-01), McElvain et al.
patent: 2004/0261044 (2004-12-01), Yonezawa
patent: 2005/0050496 (2005-03-01), Kovacs et al.
patent: 2005/0066297 (2005-03-01), Kalafala et al.
patent: 2005/0246117 (2005-11-01), Hathaway et al.

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