Electrical computers and digital processing systems: support – Computer power control
Reexamination Certificate
2000-09-29
2004-08-03
Lee, Thomas (Department: 2115)
Electrical computers and digital processing systems: support
Computer power control
C711S104000, C711S105000, C711S167000
Reexamination Certificate
active
06772352
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a memory system, and more specifically, to a power management memory system having high performance.
2. Discussion of the Related Art
In order to prevent potentially damaging power consumption, manufacturers and vendors of memory devices, such as dynamic random access memory (DRAM) devices, prescribe specifications for the safe operation of the memory devices. These specifications are often created based on an excessive worst case scenario a memory device may encounter, and not based on the core architecture capabilities of the memory device and real-world conditions.
For example, DRAM vendors may prescribe a particular minimum and maximum time interval for issuing successive “activate” commands of row-address-strobe (RAS) banks within the same DRAM component, such as RAS bank “A”, and then a subsequent activate command on RAS bank “B”. This time interval is known as “RAS-to-RAS delay”, also called “tRRD”. However, the maximum tRRD specifications prescribed by the DRAM vendors are typically over-inflated because DRAM vendors assume that an infinite stream of activate commands will be issued to the DRAM device during its operation. Under this assumption, the DRAM vendors define an inflated interval based on this infinite access pattern, which spreads the power dissipation over more time to achieve an average power that is within a safety margin to protect the DRAM device from thermal breakdown.
However, in real-world operation of DRAM devices, infinite streams of activate commands do not occur. Rather, DRAM access utilizing activate commands occurs in “bursts”. In other words, typical DRAM access occurs with bursts of activate commands, and the activate commands are not issued in back-to-back infinite streams. Periods of inactivity occur in between these activate command bursts. But, because of the maximum tRRD specifications set forth by the DRAM vendors, which are artificially inflated, the real-world operational nature of DRAM access is not utilized in the most efficient manner possible.
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Dodd James M.
Williams Michael W.
Connolly Mark
Intel Corporation
Lee Thomas
Pillsbury & Winthrop LLP
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