Method and apparatus for reducing the power consumed by a...

Details Method and apparatus for reducing the power consumed by a... Method and apparatus for reducing the power consumed by a...

2006-06-13

2006-06-13

Cottingham, John R. (Department: 2116)

Electrical computers and digital processing systems: support

Reconfiguration

Reexamination Certificate

active

07062647

ABSTRACT:
A computer system having one or more components capable of being in either wake or sleep states includes a power manager and a voltage regulator. The power manager may generate a power state signal indicating the power state of the component, and this signal may be provided to the voltage regulator. The voltage regulator may supply power to the component. The target voltage level of the power may be dependent on both a current level of the power and the power state signal.

REFERENCES:
patent: 5919262 (1999-07-01), Kikinis et al.
patent: 5926394 (1999-07-01), Nguyen et al.
patent: 6229292 (2001-05-01), Redl et al.
patent: 6304823 (2001-10-01), Smit et al.
patent: 6697952 (2004-02-01), King
patent: 2004/0130305 (2004-07-01), Agari et al.

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